FPGA可编程逻辑器件芯片EP1SGX25CF672C5N中文规格书 - 图文

December 2004, ver. 2.2Introduction

Features

Data Sheet

The Stratix?GX family of devices is Altera’s second FPGA family to combine high-speed serial transceivers with a scalable, high-performance logic array. StratixGX devices include 4 to 20high-speed transceiver channels, each incorporating clock data recovery (CDR) technology and embedded SERDES capability at data rates of up to 3.1875 gigabits per second (Gbps). These transceivers are grouped by four-channel

transceiver blocks, and are designed for low power consumption and small die size. The StratixGX FPGA technology is built upon the Stratix architecture, and offers a 1.5-V logic array with unmatched performance, flexibility, and time-to-market capabilities. This scalable,

high-performance architecture makes StratixGX devices ideal for high-speed backplane interface, chip-to-chip, and communications protocol-bridging applications.

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Transceiver block features are as follows:●High-speed serial transceiver channels with CDR provides

500-megabits per second (Mbps) to 3.1875-Gbps full-duplexoperation●Devices are available with 4, 8, 16, or 20 high-speed serial

transceiver channels providing up to 127.5Gbps of full-duplexserial bandwidth●Support for transceiver-based protocols, including 10 Gigabit

Ethernet attachment unit interface (XAUI), Gigabit Ethernet(GigE), and SONET/SDH●Compatible with PCI Express, SMPTE 292M, Fibre Channel, and

Serial RapidIO I/O standards●Programmable differential output voltage (VOD), pre-emphasis,

and equalization settings for improved signal integrity●Individual transmitter and receiver channel power-down

capability implemented automatically by the Quartus?II

software for reduced power consumption during non-operation●Programmable transceiver-to-FPGA interface with support for

8-, 10-, 16-, and 20-bit wide data paths●1.5-V pseudo current mode logic (PCML) for 500Mbps to

3.1875Gbps●Support for LVDS, LVPECL, and 3.3-V PCML on reference

clocks and receiver input pins (AC-coupled)●Built-in self test (BIST)●Hot insertion/removal protection circuitry

StratixGX FPGA Family

Features

Table1.StratixGX Device Features

Feature

LEs

Transceiver channels

Source-synchronous channelsM512 RAM blocks (32×18bits)M4K RAM blocks (128×36bits)M-RAM blocks (4K×144bits)Total RAM bits

Digital signal processing (DSP) blocksEmbedded multipliers(1)PLLs

Note to Table1:(1)

This parameter lists the total number of 9-×9-bit multipliers for each device. For the total number of 18-×18-bit multipliers per device, divide the total number of 9-×9-bit multipliers by 2. For the total number of 36-×36-bit multipliers per device, decide the total number of 9-×9-bit multipliers by 8.

EP1SGX10CEP1SGX10D

10,5704, 82294601920,448

6484

EP1SGX25CEP1SGX25DEP1SGX25F

25,6604, 8, 163922413821,944,576

10804

EP1SGX40DEP1SGX40G

41,2508, 204538418343,423,744

141128

StratixGX devices are available in space-saving FineLine BGA? packages (refer to Tables2 and 3), and in multiple speed grades (refer to Table4). StratixGX devices support vertical migration within the same package (that is, the designer can migrate between the EP1SGX10C and EP1SGX25C devices in the 672-pin FineLine BGA package). See the StratixGX device pin tables for more information. Vertical migration means that designers can migrate to devices whose dedicated pins, configuration pins, and power pins are the same for a given package across device densities. For I/O pin migration across densities, the

designer must cross-reference the available I/O pins using the device pin-outs for all planned densities of a given package type, to identify which I/O pins it is possible to migrate. The QuartusII software can

automatically cross reference and place all pins for migration when given a device migration list.

Table2.StratixGX Package Options & I/O Pin Counts(Part 1 of2)Note(1)

Device

EP1SGX10CEP1SGX10DEP1SGX25C

672-Pin FineLine BGA

362362455

1,020-Pin FineLine BGA

StratixGX FPGA Family

High-Speed I/O Interface Functional Description

Table2.StratixGX Package Options & I/O Pin Counts(Part 2 of2)Note(1)

Device

672-Pin FineLine BGA

1,020-Pin FineLine BGA

EP1SGX25D455

607EP1SGX25F607EP1SGX40D624EP1SGX40G624

Note to Table2:(1)

The number of I/O pins listed for each package includes dedicated clock pins and

dedicated fast I/O pins. However, these numbers do not include high-speed or clock reference pins for high-speed I/O standards.

Table3.StratixGX FineLine BGA Package Sizes

Dimension

672 Pin

1,020 Pin

Pitch (mm)1.001.00Area (mm2)

7291,089Length×width (mm×mm)

27×27

33×33

Table4.StratixGX Device Speed Grades

Device

672-Pin FineLine BGA

1,020-pin FineLine BGA

EP1SGX10-5, -6, -7EP1SGX25-5, -6, -7

-5, -6, -7EP1SGX40

-5, -6, -7

The StratixGX device family supports high-speed serial transceiver blocks with CDR circuitry as well as source-synchronous interfaces. The channels on the right side of the device use an embedded circuit

dedicated for receiving and transmitting high-speed serial data streams to and from the system board. These channels are clustered in a

four-channel serial transceiver building block and deliver high-speed bidirectional point-to-point data transmissions to provide up to

3.1875Gbps of full-duplex data transmission per channel. The channels on the left side of the device support source-synchronous data transfers at up to 1 Gbps using LVDS, LVPECL, 3.3-V PCML, or HyperTransport technology I/O standards. Figure1 shows the StratixGX I/O blocks. The differential source-synchronous serial interface is described in

“Principles of SERDES Operation” on page47 and the high-speed serial interface is described in “Transceiver Blocks” on page8.

FPGA Functional Description

Figure1.StratixGX I/O Blocks

DQST9PLL7Note(1)

DQST59PLL510DQST4PLL11DQST3DQST2Bank 4DQST8DQST7Bank 3DQST6DQST1DQST0VREF1B3VREF2B3VREF3B3VREF4B3VREF5B3VREF1B4VREF2B4VREF3B4VREF4B4VREF5B4VREF1B2VREF2B2VREF3B2VREF4B2I/O Bank 13 (5)LVDS, LVPECL, 3.3-V PCML, and HyperTransport I/O Blockand Regular I/O Pins (3)Bank 2(4)I/O Banks 3, 4, 9 & 10 Support All Single-Ended I/O Standards (2)I/O Bank 14 (5)PLL1PLL2VREF1B1VREF2B1VREF3B1VREF4B1I/O Banks 1 and 2 Support AllSingle-Ended I/O Standards Except Differential HSTL Output Clocks, Differential SSTL-2 Output Clocks, HSTL Class II, GTL, SSTL-18 Class II, PCI, PCI-X, and AGP 1×/2× 1.5-V PCML (5)I/O Bank 17 (5)Bank 1(4)LVDS, LVPECL, 3.3-V PCML, and HyperTransport I/O Blockand Regular I/O Pins (3)I/O Banks 7, 8, 11 & 12 Support All Single-Ended I/O Standards (2)I/O Bank 16 (5)I/O Bank 15 (5)Bank 811DQSB6DQSB512PLL12DQSB4DQSB3Bank 7VREF5B7VREF4B7VREF3B7VREF2B7VREF1B7VREF5B8VREF4B8VREF3B8VREF2B8VREF1B8PLL8DQSB9DQSB8DQSB7PLL6DQSB2DQSB1DQSB0Notes to Figure1:(1)(2)(3)(4)(5)

Figure1 is a top view of the StratixGX silicon die.

Banks 9 through 12 are enhanced PLL external clock output banks.

If the high-speed differential I/O pins are not used for high-speed differential signaling, they can support all of the I/O standards except HSTL class I and II, GTL, SSTL-18 Class II, PCI, PCI-X, and AGP 1×/2×.

For guidelines for placing single-ended I/O pads next to differential I/O pads, see the Selectable I/O Standards inStratix & StratixGX Devices chapter in the Stratix Device Handbook, Volume 2.

These I/O banks in StratixGX devices also support the LVDS, LVPECL, and 3.3-V PCML I/O standards on reference clocks and receiver input pins (AC coupled).

FPGA Functional Description

StratixGX devices contain a two-dimensional row- and column-based architecture to implement custom logic. A series of column and row interconnects of varying length and speed provide signal interconnects between logic array blocks (LABs), memory block structures, and DSP blocks.