Chapter 1:Introduction to the RocketIO GTX Transceiver
Table 1-5:GTX_DUAL Attribute Summary (Cont’d)Attribute
TypeBoolean
Description
Section (Page)
CLK_COR_KEEP_IDLE_0CLK_COR_KEEP_IDLE_1CLK_COR_MAX_LAT_0CLK_COR_MAX_LAT_1CLK_COR_MIN_LAT_0CLK_COR_MIN_LAT_1CLK_COR_PRECEDENCE_0CLK_COR_PRECEDENCE_1
Controls whether the elastic buffer
Configurable Clock
must retain at least one clock correction
Correction (page213)
sequence in the byte stream.
Specifies the maximum elastic buffer latency.
Specifies the minimum elastic buffer latency.
Determines whether clock correction or channel bonding takes precedence when both operations are triggered at the same time. Set to TRUE to give clock correction precedence.Specifies the minimum number of RXUSRCLK cycles without clock correction that must occur between successive clock corrections.
Configurable Clock Correction (page213)Configurable Clock Correction (page214)
IntegerInteger
Boolean
Configurable Clock Correction (page214)
CLK_COR_REPEAT_WAIT_0CLK_COR_REPEAT_WAIT_1CLK_COR_SEQ_1_1_0CLK_COR_SEQ_1_1_1CLK_COR_SEQ_1_2_0CLK_COR_SEQ_1_2_1CLK_COR_SEQ_1_3_0CLK_COR_SEQ_1_3_1CLK_COR_SEQ_1_4_1CLK_COR_SEQ_1_ENABLE_0CLK_COR_SEQ_1_ENABLE_1CLK_COR_SEQ_2_1_0CLK_COR_SEQ_2_1_1CLK_COR_SEQ_2_2_0CLK_COR_SEQ_2_2_1CLK_COR_SEQ_2_3_0CLK_COR_SEQ_2_3_1CLK_COR_SEQ_2_4_0CLK_COR_SEQ_2_4_1CLK_COR_SEQ_2_ENABLE_0CLK_COR_SEQ_2_ENABLE_1CLK_COR_SEQ_2_USE_0CLK_COR_SEQ_2_USE_1CLK_CORRECT_USE_0CLK_CORRECT_USE_1
Integer
Configurable Clock Correction (page214)
10-bitBinary
The CLK_COR_SEQ_1 attributes are used in conjunction with Configurable Clock CLK_COR_SEQ_1_ENABLE to define Correction (page214)clock correction sequence 1.
4-bitBinarySets which parts of clock correction sequence1 are don't cares.Configurable Clock Correction (page214)
10-bitBinary
Used in conjunction with
Configurable Clock
CLK_COR_SEQ_2_ENABLE to define
Correction (page215)
the second clock correction sequence.
4-bitBinaryBooleanBoolean
Sets which parts of clock correction sequence2 are don't cares.Determines if the second clock correction sequence is to be used.Set to TRUE to enable clock correction.
Configurable Clock Correction (page215)Configurable Clock Correction (page215)Configurable Clock Correction (page213)
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
Chapter 1:Introduction to the RocketIO GTX Transceiver
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
Chapter 3:Simulation
O : out std_logic);
end component;
begin
U1 : ROCBUF port map (I => SRP, O => GSR);//dummy process
COUNTER : process (CLOCK, ENABLE, RESET)begin....
end process COUNTER;end A
The VHDL code for this test bench, located in EX_ROCBUF_tb.vhd, is listed here:
entity EX_ROCBUF_tb isend EX_ROCBUF_tb;
architecture behavior of EX_ROCBUF_tb isdeclare component EX_ROCBUFdeclare signalsbegin
EX_ROCBUF_inst: EX_ROCBUF PORT MAP(CLOCK => CLOCK,ENABLE => ENABLE,SRP => SRP,
RESET => RESET,COUT => COUT);
Clk_generation: processBegin....
End process
reset <= '1', '0' after CLK_PERIOD * 30;SRP <= '1', '0' after CLK_PERIOD * 25;end
Further details can be found in the Synthesis and Simulation Design Guide [Ref3].
Examples
Simulation Environment Setup Example (ModelSim SE 6.1e on Linux)
This section provides an example how to set up a simulation environment for SmartModel support. This is a prerequisite for simulating designs containing GTX_DUAL tile(s).This example uses ModelSim SE 6.1e, the HDL simulator from Mentor Graphics, with RedHat Enterprise Linux 3.0 as the operating system and version 9.1i of the ISE
development system. The Synthesis and Simulation Guide provides guidelines and examples for a different HDL simulator or ISE development system(1).Use setenv to set these environment variables:
1.If there is a contradiction between this example and the documentation of the designer’s simulator, the
simulator documentation has precedence. If a newer version of the ISE development system is used, check the Xilinx website for additional information.
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
Chapter 4:Implementation
X-Ref Target - Figure 4-2Right Edge of the DieD4D3XC5VFX30T: GTX_DUAL_X0Y3XC5VFX70T: GTX_DUAL_X0Y5F1E1C1D1G2F2B2C2MGTREFCLKP_116MGTREFCLKN_116MGTRXP1_116MGTRXN1_116MGTRXP0_116MGTRXN0_116MGTTXP1_116MGTTXN1_116MGTTXP0_116MGTTXN0_116F3E3E4C3B3G3Power PinsMGTAVCCPLL_116MGTAVCC_116MGTAVCC_116MGTAVTTRX_116MGTAVTTTX_116MGTAVTTTX_116K4K3M1L1J1K1N2M2H2J2MGTREFCLKP_112MGTREFCLKN_112MGTRXP1_112MGTRXN1_112MGTRXP0_112MGTRXN0_112MGTTXP1_112MGTTXN1_112MGTTXP0_112MGTTXN0_112M3L3L4J3H3N3MGTAVCCPLL_112MGTAVCC_112MGTAVCC_112MGTAVTTRX_112MGTAVTTTX_112MGTAVTTTX_112XC5VFX30T: GTX_DUAL_X0Y2XC5VFX70T: GTX_DUAL_X0Y4T4T3V1U1R1T1W2V2P2R2MGTREFCLKP_114MGTREFCLKN_114MGTRXP1_114MGTRXN1_114MGTRXP0_114MGTRXN0_114MGTTXP1_114MGTTXN1_114MGTTXP0_114MGTTXN0_114V3U3U4R3MGTAVCCPLL_114MGTAVCC_114MGTAVCC_114MGTAVTTRX_114XC5VFX30T: GTX_DUAL_X0Y1XC5VFX70T: GTX_DUAL_X0Y3P3MGTAVTTTX_114W3MGTAVTTTX_114AB4AB3AD1AC1AA1AB1AE2AD2Y2AA2MGTREFCLKP_118MGTREFCLKN_118MGTRXP1_118MGTRXN1_118MGTRXP0_118MGTRXN0_118MGTTXP1_118MGTTXN1_118MGTTXP0_118MGTTXN0_118AD3MGTAVCCPLL_118AC3MGTAVCC_118AC4MGTAVCC_118AA3MGTAVTTRX_118AE3MGTAVTTTX_118Y3MGTAVTTTX_118XC5VFX30T: GTX_DUAL_X0Y0XC5VFX70T: GTX_DUAL_X0Y2UG198_c4_02_041507Figure 4-2:XC5VFX30T-FF665, XC5VFX70T-FF665 GTX Placement
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
FPGA可编程逻辑器件芯片XC2S300E-5FTG256I中文规格书 - 图文
