DS099 (v3.1) June 27, 2013Product Specification
DC Electrical Characteristics
In this section, specifications may be designated as Advance, Preliminary, or Production. These terms are defined as follows:?
Advance: Initial estimates are based on simulation, early characterization, and/or extrapolation from the characteristicsof other families. Values are subject to change. Although speed grades with this designation are considered relativelystable and conservative, some under-reporting might still occur. Use as estimates, not for production.
Preliminary: Based on complete early silicon characterization. Devices and speed grades with this designation areintended to give a better indication of the expected performance of production silicon. The probability of under-reporteddelays is greatly reduced compared to Advance data. Use as estimates, not for production.
Production: These specifications are approved only after silicon has been characterized over numerous productionlots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes.Parameter values are considered stable with no future changes expected.
Production-quality systems must only use FPGA designs compiled with a Production status speed file. FPGA designsusing a less mature speed file designation should only be used during system prototyping or preproduction qualification.FPGA designs with speed files designated as Advance or Preliminary should not be used in a production-qualitysystem.
Whenever a speed file designation changes, as a device matures toward Production status, rerun the latest Xilinx ISE? software on the FPGA design to ensure that the FPGA design incorporates the latest timing information and software updates.
All parameter limits are representative of worst-case supply voltage and junction temperature conditions. The following applies unless otherwise noted: The parameter values published in this module apply to all Spartan?-3 devices. AC and DC characteristics are specified using the same numbers for both commercial and industrial grades. All parameters representing voltages are measured with respect to GND.
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Mask and Fab Revisions
Some specifications list different values for one or more mask or fab revisions, indicated by the device top marking (see Package Marking, page5). The revision differences involve the power ramp rates, differential DC specifications, and DCM characteristics. The most recent revision (mask rev E and GQ fab/geometry code) is errata-free with improved specifications than earlier revisions.
Mask rev E with fab rev GQ has been shipping since 2005 (see XCN05009) and has been 100% of Xilinx Spartan-3 device shipments since 2006. SCD 0974 was provided to ensure the receipt of the rev E silicon, but it is no longer needed. Parts ordered under the SCD appended “0974” to the standard part number. For example, “XC3S50-4VQ100C” became “XC3S50-4VQ100C0974”.
Table 28:Absolute Maximum Ratings
SymbolVCCINTVCCAUXVCCOVREFVIN
Description
Internal supply voltage relative to GNDAuxiliary supply voltage relative to GNDOutput driver supply voltage relative to GNDInput reference voltage relative to GNDVoltage applied to all User I/O pins and Dual-Purpose pins relative to GND(2,4)Voltage applied to all Dedicated pins relative to GND(3)
ConditionsMin–0.5–0.5–0.5–0.5
Max1.323.003.75VCCO+0.5
4.44.3VCCAUX + 0.5
UnitsVVVVVV
Driver in a
high-impedance state
CommercialIndustrialAll temp. ranges
–0.95–0.85–0.5
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: DC and Switching Characteristics
Table 46:Timing for the IOB Three-State Path
Speed Grade
Symbol
Description
Conditions
Device
-5Max(3)
Synchronous Output Enable/Disable TimesTIOCKHZ
Time from the active transition at the OTCLK input of the Three-state Flip-Flop (TFF) to when the Output pin enters the high-impedance state
Time from the active transition at TFF’s OTCLK input to when the Output pin drives valid data
LVCMOS25, 12mA output drive, Fast slew rate
All
0.74
0.85
ns
-4Max(3)
Units
TIOCKON(2)
All0.720.82ns
Asynchronous Output Enable/Disable TimesTGTS
Time from asserting the Global Three State LVCMOS25, 12mA (GTS) net to when the Output pin enters the output drive, Fast slew high-impedance staterate
XC3S200
XC3S400XC3S50XC3S1000XC3S1500XC3S2000XC3S4000XC3S5000
7.718.38
8.879.63
nsns
Set/Reset TimesTIOSRHZ
Time from asserting TFF’s SR input to when LVCMOS25, 12mA
output drive, Fast slew the Output pin enters a high-impedance
ratestate
Time from asserting TFF’s SR input at TFF
to when the Output pin drives valid data
All
1.55
1.78
ns
TIOSRON(2)
XC3S200XC3S400XC3S50XC3S1000XC3S1500XC3S2000XC3S4000XC3S5000
2.242.91
2.573.34
nsns
Notes:
1.2.3.
The numbers in this table are tested using the methodology presented in Table48 and are based on the operating conditions set forth inTable32 and Table35.
This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. When this is true, add the appropriate Output adjustment from Table47.For minimums, use the values reported by the Xilinx timing analyzer.
Table 47:Output Timing Adjustments for IOB
Add the Adjustment Below
Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the
Following Signal Standard (IOSTANDARD)
-5
Speed Grade
-4
Units
Single-Ended StandardsGTLGTL_DCIGTLPGTLP_DCIHSLVDCI_15HSLVDCI_18
00.130.030.231.510.81
0.020.150.040.271.740.94
nsnsnsnsnsns
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: DC and Switching Characteristics
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: DC and Switching Characteristics
Digital Clock Manager (DCM) Timing
For specification purposes, the DCM consists of three key components: the Delay-Locked Loop (DLL), the Digital Frequency Synthesizer (DFS), and the Phase Shifter (PS).
Aspects of DLL operation play a role in all DCM applications. All such applications inevitably use the CLKIN and the CLKFB inputs connected to either the CLK0 or the CLK2X feedback, respectively. Thus, specifications in the DLL tables (Table58 and Table59) apply to any application that only employs the DLL component. When the DFS and/or the PS components are used together with the DLL, then the specifications listed in the DFS and PS tables (Table60 through Table63) supersede any corresponding ones in the DLL tables. DLL specifications that do not change with the addition of DFS or PS functions are presented in Table58 and Table59.
Period jitter and cycle-cycle jitter are two (of many) different ways of characterizing clock jitter. Both specifications describe statistical variation from a mean value.
Period jitter is the worst-case deviation from the average clock period of all clock cycles in the collection of clock periods sampled (usually from 100,000 to more than a million samples for specification purposes). In a histogram of period jitter, the mean value is the clock period.
Cycle-cycle jitter is the worst-case difference in clock period between adjacent clock cycles in the collection of clock periods sampled. In a histogram of cycle-cycle jitter, the mean value is zero.
Delay-Locked Loop (DLL)
Table 58:Recommended Operating Conditions for the DLL
Speed Grade
Symbol
Input Frequency RangesFCLKIN
CLKIN_FREQ_DLL_LFCLKIN_FREQ_DLL_HF
Input Pulse RequirementsCLKIN_PULSE
CLKIN pulse width as a
percentage of the CLKIN period
FCLKIN ≤ 100 MHzFCLKIN > 100 MHz
LowHighAllAll
40E%––––
Allowable variation of off-chip feedback delay from the DCM output to the CLKFB input
–
60U%
40E%–––––
60U%
--pspsnsns
Frequency for the CLKIN input
LowHigh
18(2)48
167(3)280(3)
18(2)48
167(3)280(3)(4)
MHzMHz
Description
Frequency Mode/FCLKIN Range
Min
-5Max
Min
-4Max
Units
Input Clock Jitter Tolerance and Delay Path Variation(5)CLKIN_CYC_JITT_DLL_LFCLKIN_CYC_JITT_DLL_HFCLKIN_PER_JITT_DLL_LF CLKIN_PER_JITT_DLL_HF CLKFB_DELAY_VAR_EXT
Cycle-to-cycle jitter at the CLKIN input
Period jitter at the CLKIN input
±300±150±1±1
±300±150±1±1
Notes:
1.DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
2.3.4.5.
The DFS, when operating independently of the DLL, supports lower FCLKIN frequencies. See Table60.
The CLKIN_DIVIDE_BY_2 attribute can be used to increase the effective input frequency range up to FBUFG. When set to TRUE,CLKIN_DIVIDE_BY_2 divides the incoming clock frequency by two as it enters the DCM.
Industrial temperature range devices have additional requirements for continuous clocking, as specified in Table64.CLKIN input jitter beyond these limits may cause the DCM to lose lock. See UG331 for more details.
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: DC and Switching Characteristics
Table 59:Switching Characteristics for the DLL
Speed Grade
Symbol
Description
Frequency Mode /FCLKIN Range
Device
Min
-5Max
167
-4Min
18
UnitsMax
167
MHz
Output Frequency Ranges
CLKOUT_FREQ_1X_LF
Frequency for the CLK0,
CLK90, CLK180, and CLK270 outputs
Frequency for the CLK0 and CLK180 outputs
Frequency for the CLK2X and CLK2X180 outputsFrequency for the CLKDV output
Low
All
18
CLKOUT_FREQ_1X_HFCLKOUT_FREQ_2X_LF(3)CLKOUT_FREQ_DV_LFCLKOUT_FREQ_DV_HF
HighLowLowHighAll
All
4836
1.125
280334110185±100±150±150±150±200±150
4836
1.125
280334110185±100±150±150±150±200±150
MHzMHzMHzMHzpspspspspsps
33
Output Clock Jitter(4)
CLKOUT_PER_JITT_0CLKOUT_PER_JITT_90CLKOUT_PER_JITT_180CLKOUT_PER_JITT_270CLKOUT_PER_JITT_2XCLKOUT_PER_JITT_DV1
Period jitter at the CLK0 output
Period jitter at the CLK90 output
Period jitter at the CLK180 output
Period jitter at the CLK270 output
Period jitter at the CLK2X and CLK2X180 outputsPeriod jitter at the CLKDV output when performing integer division
Period jitter at the CLKDV output when performing non-integer division
All
––––––
––––––
CLKOUT_PER_JITT_DV2–±300–±300ps
Duty Cycle
CLKOUT_DUTY_CYCLE_DLL(5)Duty cycle variation for the
CLK0, CLK90, CLK180,
CLK270, CLK2X, CLK2X180, and CLKDV outputs
XC3S50XC3S200XC3S400XC3S1000XC3S1500XC3S2000XC3S4000XC3S5000
––––––––––
±150±150±250±400±400±400±400±400
––––––––––
±150±150±250±400±400±400±400±400
pspspspspspspsps
Phase Alignment
CLKIN_CLKFB_PHASECLKOUT_PHASE
Phase offset between the CLKIN and CLKFB inputsPhase offset between any two DLL outputs (except CLK2X and CLK0)
Phase offset between the CLK2X and CLK0 outputs
All
All
±150±140
±150±140
psps
–±250–±250ps
DS099 (v3.1) June 27, 2013Product Specification
FPGA可编程逻辑器件芯片XCZU15EG-3FFVB1156E中文规格书 - 图文
