Semiconductor memory device
申请(专利)号： JP19940097511
专利号： JP3667787B2 主分类号： G11C11/407 申请权利人： 株式会社ルネサス
テクノロジ 公开国代码： JP 优先权国家： JP
摘 要：
Level converter converts a word line group specifying signal, which is sent from a row decoder and has amplitude of a power supply potential Vcc and a ground potential GND, into mutually complementary logic signals WD and ZWD of a high voltage Vpp and a
negative potential Vbb. An RX decoder decodes an address signal to output a signal of an amplitude of (Vpp-Vbb) specifying a word line in a word line group. A word driver provided
corresponding to each word line transmits a word line specifying signal or a negative potential to the corresponding word line in accordance with signals WD and ZWD sent from a level converting circuit. The nonselected word line receives negative potential Vbb from a word driver. The selected word line receives high voltage Vpp from the word driver. It is possible to suppress a channel leak current at a memory transistor in the nonselected
memory cell, which may be caused by the potential change of the word line and/or bit line, and a charge holding
characteristic of the memory cell can be
申请日： 1994-05-11 公开公告日： 2005-07-06
分类号： G11C11/407 发明设计人： 冨嶋 茂樹;
有本 和民 申请国代码： JP
优先权： 19940511 JP
9751194
摘 要 附 图：
improved. 主权项：
各々が行列状に配列される複数のメモリセルを有する複数のメモリブロック、 各前記メモリブロックにおいて各前記行に対応して配置され、各々に対応の行のメモリセルが接続する複数のワード線、および
权 利 要 求 说 明 书
【Semiconductor memory device】的权利说明书内容是......请下载后查看
Semiconductor memory device
