Data Sheet
ADuM1410/ADuM1411/ADuM1412
FEATURES
Low power operation 5 V operation
1.3 mA per channel maximum at 0 Mbps to 2 Mbps 4.0 mA per channel maximum at 10 Mbps 3 V operation
0.8 mA per channel maximum at 0 Mbps to 2 Mbps 1.8 mA per channel maximum at 10 Mbps Bidirectional communication 3 V/5 V level translation
High temperature operation: 105°C Up to 10 Mbps data rate (NRZ)
Programmable default output state
High common-mode transient immunity: >25 kV/μs 16-lead, RoHS compliant, SOIC wide body package Safety and regulatory approvals
UL recognition: 3750 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice 5A VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 VIORM = 560 V peak
TüV approval: IEC/EN 60950-1
APPLICATIONS
General-purpose multichannel isolation SPI interface/data converter isolation RS-232/RS-422/RS-485 transceivers Industrial field bus isolation
GENERAL DESCRIPTION
The ADuM1410/ADuM1411/ADuM14121 are four-channel digital isolators based on Analog Devices, Inc., iCoupler? technology. Combining high speed CMOS and monolithic air core transformer technologies, these isolation components provide outstanding performance characteristics superior to alternatives such as optocoupler devices.
By avoiding the use of LEDs and photodiodes, iCoupler devices remove the design difficulties commonly associated with opto-couplers. The usual concerns that arise with optocouplers, such as uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects, are eliminated with the simple iCoupler digital interfaces and stable performance characteristics. The need for external drivers and other discrete components is eliminated with these iCoupler products. Furthermore, iCoupler
1
Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329.
FUNCTIONAL BLOCK DIAGRAMS VDD1116VDD2GNDADuM14101215GND2VIA3ENCODEDECODE14VOAVIB4ENCODEDECODE13VOBVIC5ENCODEDECODE12VOCVID6ENCODEDECODE11VODDISABLE710CTRL2100-GND189GND028560Figure 1. ADuM1410
VDD11GNDADuM141116VDD21215GND2VIA3ENCODEDECODE14VOAVIB4ENCODEDECODE13VOBVIC5ENCODEDECODE12VOCVOD6DECODEENCODE11VIDCTRL1710CTRL2200-GND189GND028560Figure 2. ADuM1411
VDD1116VDD2GNDADuM14121215GND2VIA3ENCODEDECODE14VOAVIB4ENCODEDECODE13VOBVOC5DECODEENCODE12VICVOD6DECODEENCODE11VIDCTRL1710CTRL2300-GND9GND01828560Figure 3. ADuM1412
devices consume one-tenth to one-sixth the power of optocou-plers at comparable signal data rates.
The ADuM1410/ADuM1411/ADuM1412 isolators provide four independent isolation channels in a variety of channel configu-rations and data rates (see the Ordering Guide) up to 10 Mbps. All models operate with the supply voltage on either side ranging from 2.7 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling voltage translation functionality across the isolation barrier. All products also have a default output control pin. This allows the user to define the logic state the outputs are to adopt in the absence of the input power. Unlike other optocoupler alternatives, the ADuM1410/ADuM1411/ ADuM1412 isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions.
Data Sheet
Parameter
ADuM1410BRWZ/ADuM1411BRWZ/ ADuM1412BRWZ
Minimum Pulse Width2 Maximum Data Rate3 Propagation Delay4
Pulse Width Distortion, |tPLH ? tPHL|4
Change vs. Temperature Propagation Delay Skew5
Channel-to-Channel Matching, Codirectional Channels6
Channel-to-Channel Matching, Opposing-Directional Channels6 All Models
Output Rise/Fall Time (10% to 90%) 5 V/3 V Operation 3 V/5 V Operation
Common-Mode Transient Immunity at Logic High Output7
Common-Mode Transient Immunity at Logic Low Output7 Refresh Rate
5 V/3 V Operation 3 V/5 V Operation Input Enable Time8 Input Disable Time8
Input Dynamic Supply Current per Channel9 5 V Operation
3 V Operation
0.07
Output Dynamic Supply Current per Channel9 5 V Operation 3 V Operation
0.02
1
ADuM1410/ADuM1411/ADuM1412
Symbol
Min
Typ
Max Unit Test Conditions/Comments
PW tPHL, tPLH PWD tPSK tPSKCD tPSKOD tR/tF
2.5 2.5
|CMH| |CML| fr
25 25
35 35 1.2 1.1 2.0 5.0
10 25
35 5
100 ns
Mbps 60 ns 5 ns
ps/°C 30 ns 5 6
ns ns
CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels
ns ns
VIx = VDD1 or VDD2, VCM = 1000 V, kV/μs transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V, transient kV/μs magnitude = 800 V Mbps Mbps μs VIA, VIB, VIC, VID = 0 V or VDD1 μs VIA, VIB, VIC, VID = 0 V or VDD1
tENABLE
tDISABLE IDDI (D)
0.12
mA/ Mbps mA/ Mbps IDDO (D)
0.04
mA/ Mbps mA/ Mbps
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1410/ADuM1411/ADuM1412 channel configurations. 2
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4
tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5
tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7
|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. |CML| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8
Input enable time is the duration from when VDISABLE is set low until the output states are guaranteed to match the input states in the absence of any input data logic transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when VDISABLE is set high until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL2 logic state (see Table 14). 9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate.
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Data Sheet ADuM1410/ADuM1411/ADuM1412
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD11GND1*2VIA3VIB4VIC5VID6DISABLE7GND1*81615VDD2GND2*VOAVOBVOCVODCTRL2GND2*06580-004ADuM1410TOP VIEW(Not to Scale)14131211109*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTHTO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLYCONNECTED. CONNECTING BOTH TO GND2 IS RECOMMENDED.Figure 5. ADuM1410 Pin Configuration
Table 11. ADuM1410 Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Mnemonic Description VDD1 Supply Voltage for Isolator Side 1 (2.7 V to 5.5 V). GND1 Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is
recommended.
VIA Logic Input A. VIB Logic Input B. VIC Logic Input C. VID Logic Input D. DISABLE Input Disable. Disables the isolator inputs and halts the dc refresh circuits. Outputs take on the logic state
determined by CTRL2.
GND1 Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is
recommended.
GND2 Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is
recommended.
CTRL2 Default Output Control. Controls the logic state the outputs assume when the input power is off. VOA, VOB, VOC, and
VOD outputs are high when CTRL2 is high or disconnected and VDD1 is off. VOA, VOB, VOC, and VOD outputs are low when CTRL2 is low and VDD1 is off. When VDD1 power is on, this pin has no effect.
VOD Logic Output D. VOC Logic Output C. VOB Logic Output B. VOA Logic Output A. GND2 Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is
recommended.
VDD2 Supply Voltage for Isolator Side 2 (2.7 V to 5.5 V).
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Data Sheet ADuM1410/ADuM1411/ADuM1412
Rev. M | Page of 22
Data Sheet
APPLICATIONS INFORMATION
PC BOARD LAYOUT
The ADuM1410/ADuM1411/ADuM1412 digital isolators require no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins (see Figure 16). Bypass capacitors are most conveniently connected between Pin 1 and Pin 2 for VDD1, and between Pin 15 and Pin 16 for VDD2. The capacitor value should be between 0.01 μF and 0.1 μF. The total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. Bypassing between Pin 1 and Pin 8 and between Pin 9 and Pin 16 should also be considered unless both ground pins on each package are connected together close to the package.
VDD1GND1VIAVIBVICVIDDISABLEGND1VDD2GND2VOAVOBVOCVODCTRL2GND2ADuM1410/ADuM1411/ADuM1412
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder using the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than ~1 μs, a periodic set of refresh pulses indicative of the correct input state is sent to ensure dc correctness at the output. If the decoder receives no internal pulses of more than approximately 5 μs, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see Table 14) by the watchdog timer circuit.
The magnetic field immunity of the ADuM1410/ADuM1411/ ADuM1412 is determined by the changing magnetic field, which induces a voltage in the transformer’s receiving coil large enough to either falsely set or reset the decoder. The following analysis defines the conditions under which this can occur. The 3 V operating condition of the ADuM1410/ADuM1411/ADuM1412 is examined because it represents the most susceptible mode of operation.
The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by
V = (?dβ/dt) ∑ π rn2; n = 1, 2, … , N
where:
β is magnetic flux density (gauss).
rn is the radius of the nth turn in the receiving coil (cm). N is the number of turns in the receiving coil.
Given the geometry of the receiving coil in the ADuM1410/ ADuM1411/ADuM1412 and an imposed requirement that the induced voltage be, at most, 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field at a given frequency can be calculated. The result is shown in Figure 18.
100MAXIMUM ALLOWABLE MAGNETIC FLUXDENSITY (kgauss)ADuM1410Figure 16. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, it is important to minimize board coupling across the isolation barrier. Furthermore, users should design the board layout so that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this can cause voltage differentials between pins exceeding the absolute maximum ratings of the device, thereby leading to latch-up or permanent damage. See the AN-1109 Application Note for board layout guidelines.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The input-to-output propagation delay time for a high-to-low transition may differ from the propagation delay time of a low-to-high transition.
INPUT (VIx)50%tPLHOUTPUT (VOx)tPHL50580-01706580-01610Figure 17. Propagation Delay Parameters
Pulse width distortion is the maximum difference between these two propagation delay values and an indication of how accurately the timing of the input signal is preserved.
Channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single ADuM1410/ADuM1411/ADuM1412 component.
Propagation delay skew refers to the maximum amount the propagation delay differs between multiple ADuM1410/ ADuM1411/ADuM1412 components operating under the same conditions.
10.10.0110k100k1M10MMAGNETIC FIELD FREQUENCY (Hz)100MFigure 18. Maximum Allowable External Magnetic Flux Density
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06580-0180.0011k
MEMORY存储芯片ADUM1411ARWZ-RL中文规格书 - 图文
