Program Operations
Successful programming requires the addressed block to be unlocked. If the block islocked down, WP# must be de-asserted and the block must be unlocked before at-tempting to program the block. Attempting to program a locked block causes a programerror (SR4 and SR1 set) and termination of the operation. See Security Modes for detailson locking and unlocking blocks.
Word Programming (40h)
Word programming operations are initiated by writing the WORD PROGRAM SETUPcommand to the device (see the Command Codes and Definitions table). This is fol-lowed by a second write to the device with the address and data to be programmed. Thedevice outputs status register data when read (see the Word Program Flowchart). VPPmust be above VPPLK, and within the specified VPPL MIN/MAX values.
During programming, the device executes a sequence of internally-timed events thatprogram the desired data bits at the addressed location, and verifies that the bits aresufficiently programmed. Programming the array changes 1s to 0s. Memory array bitsthat are 0s can be changed to 1s only by erasing the block (see Erase Operations).The status register can be examined for programming progress and errors by reading atany address. The device remains in the read status register state until another com-mand is written to the device.
SR7 indicates the programming status while the sequence executes. Commands thatcan be issued to the device during programming are PROGRAM SUSPEND, READ STA-TUS REGISTER, READ DEVICE IDENTIFIER, READ CFI, and READ ARRAY (this returnsunknown data).
When programming has finished, SR4 (when set) indicates a programming failure. IfSR3 is set, the device could not perform the WORD PROGRAMMING operation becauseVPP was outside of its acceptable limits. If SR1 is set, the WORD PROGRAMMING opera-tion attempted to program a locked block, causing the operation to abort.
Before issuing a new command, the status register contents should be examined andthen cleared using the CLEAR STATUS REGISTER command. Any valid command canfollow, when word programming has completed.
Buffered Programming (E8h, D0h)
The device features a 512-word buffer to enable optimum programming performance.For buffered programming, data is first written to an on-chip write buffer. Then the buf-fer data is programmed into the array in buffer-size increments. This can improve sys-tem programming performance significantly over non-buffered programming.When the BUFFERED PROGRAMMING SETUP command is issued, status register in-formation is updated and reflects the availability of the buffer. SR7 indicates bufferavailability: if set, the buffer is available; if cleared, the buffer is not available.
Note: The device default state is to output SR data after the BUFFERED PROGRAM-MING SETUP command. CE# and OE# LOW drive device to update status register. It isnot allowed to issue 70h to read SR data after E8h command; otherwise, 70h would becounted as word count.
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Program Operations
On the next write, a word count is written to the device at the buffer address. This tellsthe device how many data words will be written to the buffer, up to the maximum sizeof the buffer.
On the next write, a device start address is given along with the first data to be written tothe flash memory array. Subsequent writes provide additional device addresses and da-ta. All data addresses must lie within the start address plus the word count. Optimumprogramming performance and lower power usage are obtained by aligning the startingaddress at the beginning of a 512-word boundary (A[9:1] = 0x00 for Easy BGA and TSOP,A[8:0] for QUAD+ package; see Part Numbering Information). The maximum buffer sizewould be 256-word if the misaligned address range is crossing a 512-word boundaryduring programming.
After the last data is written to the buffer, the BUFFERED PROGRAMMING CONFIRMcommand must be issued to the original block address. The device begins to programbuffer contents to the array. If a command other than the BUFFERED PROGRAMMINGCONFIRM command is written to the device, a command sequence error occurs andSR[7,5,4] are set. If an error occurs while writing to the array, the device stops program-ming, and SR[7,4] are set, indicating a programming failure.
When buffered programming has completed, additional buffer writes can be initiatedby issuing another BUFFERED PROGRAMMING SETUP command and repeating thebuffered program sequence. Buffered programming may be performed with VPP = VPPLor VPPH (see Operating Conditions for limitations when operating the device with VPP =VPPH).
If an attempt is made to program past an erase-block boundary using the BUFFEREDPROGRAM command, the device aborts the operation. This generates a command se-quence error, and SR[5,4] are set.
If buffered programming is attempted while VPP is at or below VPPLK, SR[4,3] are set. Ifany errors are detected that have set status register bits, the status register should becleared using the CLEAR STATUS REGISTER command.
Buffered Enhanced Factory Programming (80h, D0h)
Buffered enhanced factory programming (BEFP) speeds up multilevel cell (MLC) pro-gramming. The enhanced programming algorithm used in BEFP eliminates traditionalprogramming elements that drive up overhead in device programmer systems.
BEFP consists of three phases: setup, program/verify, and exit (see the BEFP Flowchart).It uses a write buffer to spread MLC program performance across 512 data words. Verifi-cation occurs in the same phase as programming to accurately program the cell to thecorrect bit state.
A single two-cycle command sequence programs the entire block of data. This en-hancement eliminates three write cycles per buffer: two commands and the word countfor each set of 512 data words. Host programmer bus cycles fill the device write bufferfollowed by a status check. SR0 indicates when data from the buffer has been program-med into sequential array locations.
Following the buffer-to-flash array programming sequence, the device increments in-ternal addressing to automatically select the next 512-word array boundary. This aspectof BEFP saves host programming equipment the address bus setup overhead.
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Erase Operations
Erase Operations
BLOCK ERASE Command
ERASE operations are performed on a block basis. An entire block is erased each time aBLOCK ERASE command sequence is issued, and only one block is erased at a time.When a block is erased, each bit within that block reads as a logical 1.
A BLOCK ERASE operation is initiated by writing the BLOCK ERASE SETUP commandto the address of the block to be erased, followed by the BLOCK ERASE CONFIRM com-mand. If the device is placed in standby (CE# de-asserted) during a BLOCK ERASE oper-ation, the device completes the operation before entering standby. The VPP value mustbe above VPPLK and the block must be unlocked.
During a BLOCK ERASE operation, the device executes a sequence of internally-timedevents that conditions, erases, and verifies all bits within the block. Erasing the arraychanges the value in each cell from a 1 to a 0. Memory block array cells that with a valueof 1 can be changed to 0 only by programming the block.
The status register can be examined for block erase progress and errors by reading anyaddress. The device remains in the read status register state until another command iswritten. SR0 indicates whether the addressed block is erasing. SR7 is set upon erasecompletion.
SR7 indicates block erase status while the sequence executes. When the BLOCK ERASEoperation has completed, SR5 = 1 (set) indicates an erase failure. SR3 = 1 indicates thatthe device could not perform the BLOCK ERASE operation because VPP was outside ofits acceptable limits. SR1 = 1 indicates that the BLOCK ERASE operation attempted toerase a locked block, causing the operation to abort.
Before issuing a new command, the status register contents should be examined andthen cleared using the CLEAR STATUS REGISTER command. Any valid command canfollow after the BLOCK ERASE operation has completed.
The BLOCK ERASE operation is aborted by performing a reset or powering down thedevice. In either case, data integrity cannot be ensured, and it is recommended to eraseagain the blocks aborted.
BLANK CHECK Command
The BLANK CHECK operation determines whether a specified main block is blank; thatis, completely erased. Other than a BLANK CHECK operation, only a BLOCK ERASE op-eration can ensure a block is completely erased. BLANK CHECK is especially usefulwhen a BLOCK ERASE operation is interrupted by a power loss event.
A BLANK CHECK operation can apply to only one block at a time. The only operationallowed simultaneously is a READ STATUS REGISTER operation. SUSPEND and RE-SUME operations and a BLANK CHECK operation are mutually exclusive.
A BLANK CHECK operation is initiated by writing the BLANK CHECK SETUP commandto the block address, followed by the CHECK CONFIRM command. When a successfulcommand sequence is entered, the device automatically enters the read status state.The device then reads the entire specified block and determines whether any bit in theblock is programmed or over-erased.
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Erase Operations
BLANK CHECK operation progress and errors are determined by reading the status reg-ister at any address within the block being accessed. SR7 = 0 is a BLANK CHECK busystatus. SR7 = 1 is a BLANK CHECK operation complete status. The status register shouldbe checked for any errors and then cleared. If the BLANK CHECK operation fails, mean-ing the block is not completely erased, SR5 = 1. CE# or OE# toggle (during polling) up-dates the status register.
The READ STATUS REGISTER command must always be followed by a CLEAR STATUSREGISTER command. The device remains in status register mode until another com-mand is written to the device. Any command can follow once the BLANK CHECK com-mand is complete.
ERASE SUSPEND Command
The ERASE SUSPEND command suspends a BLOCK ERASE operation that is in pro-gress, enabling access to data in memory locations other than the one being erased. TheERASE SUSPEND command can be issued to any device address. A BLOCK ERASE oper-ation can be suspended to perform a WORD or BUFFER PROGRAM operation, or aREAD operation within any block except the block that is erase suspended.
When a BLOCK ERASE operation is executing, issuing the ERASE SUSPEND commandrequests the device to suspend the erase algorithm at predetermined points. The devicecontinues to output status register data after the ERASE SUSPEND command is issued.Block erase is suspended when SR[7,6] are set.
To read data from the device (other than an erase-suspended block), the READ ARRAYcommand must be issued. During erase suspend, a PROGRAM command can be issuedto any block other than the erase-suspended block. Block erase cannot resume untilprogram operations initiated during erase suspend complete. READ ARRAY, READ STA-TUS REGISTER, READ DEVICE IDENTIFIER, READ CFI, and ERASE RESUME are validcommands during erase suspend. Additionally, CLEAR STATUS REGISTER, PROGRAM,PROGRAM SUSPEND, BLOCK LOCK, BLOCK UNLOCK, and BLOCK LOCK DOWN arevalid commands during an ERASE SUSPEND operation.
During an erase suspend, de-asserting CE# places the device in standby, reducing activecurrent. VPP must remain at a valid level, and WP# must remain unchanged while inerase suspend. If RST# is asserted, the device is reset.
ERASE RESUME Command
The ERASE RESUME command instructs the device to continue erasing, and automati-cally clears SR[7,6]. This command can be written to any address. If status register errorbits are set, the status register should be cleared before issuing the next instruction.RST# must remain de-asserted.
Erase Protection
When VPP = VIL, absolute hardware erase protection is provided for all device blocks. IfVPP is at or below VPPLK, ERASE operations halt and SR3 is set indicating a VPP-level er-ror.
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Security Operations
Selectable OTP Blocks
The OTP security feature on the device is backward-compatible to the earlier genera-tion devices. Contact your local Micron representative for details about its implementa-tion.
Password Access
The password access is a security enhancement offered on the device. This feature pro-tects information stored in array blocks by preventing content alteration or reads until avalid 64-bit password is received. The password access may be combined with nonvola-tile protection and/or volatile protection to create a multi-tiered solution.Contact your Micron sales office for further details concerning password access.
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MEMORY存储芯片N25Q064A13ESF40F中文规格书 - 图文
