MEMORY存储芯片ADM3078EARZ-REEL7中文规格书 - 图文

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Error Management

Each NAND Flash die (LUN) is specified to have a minimum number of valid blocks(NVB) of the total available blocks. This means the die (LUNs) could have blocks thatare invalid when shipped from the factory. An invalid block is one that contains at leastone page that has more bad bits than can be corrected by the minimum required ECC.Additional blocks can develop with use. However, the total number of available blocksper die (LUN) will not fall below NVB during the endurance life of the product.

Although NAND Flash memory devices could contain bad blocks, they can be used

quite reliably in systems that provide bad block management and error-correction algo-rithms. This type of software environment ensures data integrity.

Internal circuitry isolates each block from other blocks, so the presence of a bad blockdoes not affect the operation of the rest of the NAND Flash array.

NAND Flash devices are shipped from the factory erased. The factory identifies invalidblocks before shipping by attempting to program the bad block mark into every loca-tion in the first page of each invalid block. It may not be possible to program every loca-tion with the bad block mark. However, the first spare area location in each bad block isguaranteed to contain the bad block mark. This method is compliant with ONFI FactoryDefect Mapping requirements. See the following table for the first spare area locationand the bad block mark.

System software should check the first spare area location on the first page of eachblock prior to performing any PROGRAM or ERASE operations on the NAND Flash de-vice. A bad block table can then be created, enabling system software to map aroundthese areas. Factory testing is performed under worst-case conditions. Because invalidblocks could be marginal, it may not be possible to recover this information if the blockis erased.

Over time, some memory locations may fail to program or erase properly. In order toensure that data is stored properly over the life of the NAND Flash device, the followingprecautions are required:

?Always check status after a PROGRAM or ERASE operation

?Under typical conditions, use the minimum required ECC (see table below)?Use bad block management and wear-leveling algorithms

The first block (physical block address 00h) for each CE# is guaranteed to be validwith ECC when shipped from the factory.Table 21: Error Management Details

DescriptionMinimum number of valid blocks (NVB) per LUNTotal available blocks per LUNFirst spare area locationBad-block markMinimum required ECCPDF: 09005aef83b25735

m60a_4gb_ecc_nand.pdf – Rev. M 2/12 EN

Requirement40164096x8: byte 2048x16: word 1024x8: 00hx16: 0000h4-bit ECC per 528 bytes4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory

Electrical Specifications

Parameter/ConditionVoltage inputVCC supply voltageStorage temperatureShort circuit output current, I/Os1.8V3.3V1.8V3.3VTSTG–VCCSymbolVINMin–0.6–0.6–0.6–0.6–65–Max2.44.62.44.61505UnitVVVV°CmAPDF: 09005aef83b25735

m60a_4gb_ecc_nand.pdf – Rev. M 2/12 EN

4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory

Electrical Specifications – AC Characteristics and Operating

Conditions

Electrical Specifications – AC Characteristics and Operating Conditions

Table 29: AC Characteristics: Command, Data, and Address Input (3.3V)

Note 1 applies to allParameterALE to data startALE hold timeALE setup timeCE# hold timeCLE hold timeCLE setup timeCE# setup timeData hold timeData setup timeWRITE cycle timeWE# pulse width HIGHWE# pulse widthWP# transition to WE# LOWNotes:

SymboltADLtALHtALStCHtCLHtCLStCStDHtDStWCtWHtWPtWWMin705105510155720710100Max–––––––––––––UnitnsnsnsnsnsnsnsnsnsnsnsnsnsNotes22221.Operating mode timings meet ONFI timing mode 5 parameters.

2.Timing for tADL begins in the address cycle, on the final rising edge of WE#, and ends

with the first rising edge of WE# for data input.

Table 30: AC Characteristics: Command, Data, and Address Input (1.8V)

SymboltADLtALHtALStCHtCLHtCLStCStDHtDStWCtWHtWPtWWMin70510551020510251012100Max–––––––––––––UnitnsnsnsnsnsnsnsnsnsnsnsnsnsNotes22221.Operating mode timings meet ONFI timing mode 4 parameters.

2.Timing for tADL begins in the address cycle on the final rising edge of WE#, and ends

with the first rising edge of WE# for data input.

PDF: 09005aef83b25735

m60a_4gb_ecc_nand.pdf – Rev. M 2/12 EN

4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory

Electrical Specifications – AC Characteristics and Operating

Conditions

Table 31: AC Characteristics: Normal Operation (3.3V)

Note 1 applies to allParameterALE to RE# delayCE# access timeCE# HIGH to output High-ZCLE to RE# delayCE# HIGH to output holdOutput High-Z to RE# LOWREAD cycle timeRE# access timeRE# HIGH hold timeRE# HIGH to output holdRE# HIGH to WE# LOWRE# HIGH to output High-ZRE# LOW to output holdRE# pulse widthReady to RE# LOWReset time (READ/PROGRAM/ERASE)WE# HIGH to busyWE# HIGH to RE# LOWNotes:

SymboltARtCEAtCHZtCLRtCOHtIRtRCtREAtREHtRHOHtRHWtRHZtRLOHtRPtRRtRSTtWBtWHRMin10––1015020–715100–51020––60Max–2550––––16–––100–––5/10/500100–UnitnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsμsnsnsNotes2231.AC characteristics may need to be relaxed if I/O drive strength is not set to full.

2.Transition is measured ±200mV from steady-state voltage with load. This parameter is

sampled and not 100% tested.

3.The first time the RESET (FFh) command is issued while the device is idle, the device will

go busy for a maximum of 1ms. Thereafter, the device goes busy for a maximum of 5μs.

Table 32: AC Characteristics: Normal Operation (1.8V)

m60a_4gb_ecc_nand.pdf – Rev. M 2/12 EN

SymboltARtCEAtCHZtCLRtCOHtIRtRCtREAtREHtRHOHtRHWMin10––1015025–1015100Max–2550––––22–––UnitnsnsnsnsnsnsnsnsnsnsnsNotes24Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory

Asynchronous Interface Timing Diagrams

Figure 82: RESET Operation

CLECE#tWBWE#tRSTR/B#I/O[7:0]FFhRESETcommandFigure 83: READ STATUS Cycle

tCLRCLEtCLStCLHCE#tCStWPWE#tCHtCEAtWHRRE#tRHZtDS I/O[7:0]70htDHtIRtREAtRHOHStatusoutputtRPtCOHtCHZDon’t CarePDF: 09005aef83b25735

m60a_4gb_ecc_nand.pdf – Rev. M 2/12 EN