2.Intel Agilex I/O Features and Usage
UG-20244 | 2024.04.05
Related Information
AN 433: Constraining and Analyzing Source-Synchronous Interfaces
Describes techniques for constraining and analyzing source-synchronous interfaces.
Single Data Rate Input RegisterFigure 27.
Single Data Rate Input Register
Table 23.Single Data Rate Input Register .sdc Command Examples
Command Example
Description
Creates clock setting for the input clock.Instructs the Timing Analyzer to analyze thetiming of the input I/O with a 0.15 ns inputdelay.
Command
create_clockset_input_delay
create_clock -name sdr_in_clk -period\
set_input_delay -clock sdr_in_clk0.15 sdr_in_data
Full-Rate or Half-Rate DDIO Input Register
The input side of the full-rate and half-rate DDIO input registers are the same. Youcan properly constrain the system by using a virtual clock to model the off-chiptransmitter to the FPGA.
Figure 28.
Full-Rate or Half-Rate DDIO Input Register
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2.Intel Agilex I/O Features and UsageUG-20244 | 2024.04.05
Table 24.Full-Rate or Half-Rate DDIO Input Register .sdc Command Examples
Command Example
Description
Create clock setting for the virtual clock and theDDIO clock.
Command
create_clock
create_clock -name virtual_clock-period \
create_clock -name ddio_in_clk-period \
set_input_delay -clock virtual_clock0.25 ddio_in_data
set_input_delay -add_delay
-clock_fall -clock virtual_clock 0.25ddio_in_data
set_false_path -fall_from
virtual_clock -rise_to ddio_in_clkset_false_path -rise_from
virtual_clock -fall_to ddio_in_clk
set_input_delay
Instruct the Timing Analyzer to analyze the
positive clock edge and the negative clock edgeof the transfer. Note the -add_delay in thesecond set_input_delay command.
set_false_path
Instruct the Timing Analyzer to ignore thepositive clock edge to the negative edge
triggered register, and the negative clock edge tothe positive edge triggered register.
Note: The ck_hr frequency must be half the
ck_fr frequency. If the I/O PLL drivesthe clocks, you can consider using thederive_pll_clocks .sdc command.
Single Data Rate Output RegisterFigure 29.
Single Data Rate Output Register
Table 25.Single Data Rate Output Register .sdc Command Examples
Command Example
Description
Generate the source clock and the output clockto transmit.
Command
create_clock andcreate_generated_clock
create_clock -name sdr_out_clk-period \create_generated_clock -sourcesdr_out_clk -name sdr_out_outclksdr_out_outclk
set_output_delay -clock sdr_out_clk0.45 sdr_out_data
set_output_delay
Instructs the Timing Analyzer to analyze theoutput data to transmit against the outputclock to transmit.
2.3.2.5.5. Timing Closure Guidelines
For the GPIO input registers, the input I/O transfer is likely to fail hold time if you donot set the input delay chain. This failure is caused by the clock delay being largerthan the data delay.
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FPGA可编程逻辑器件芯片EP3C10U256I7中文规格书
