MEMORY存储芯片ADM3202ARNZ中文规格书 - 图文

由天下分享时间：2024/11/5 22:43:18 加入收藏我要投稿点赞

Status Register

Read Status Register

To read the status register, issue the READ STATUS REGISTER command at any address.Status register information is available at the address that the READ STATUS REGISTER,WORD PROGRAM, or BLOCK ERASE command is issued to. Status register data is auto-matically made available following a word program, block erase, or block lock com-mand sequence. Reads from the device after any of these command sequences will out-put the devices status until another valid command is written (e.g. READ ARRAY com-mand).

The status register is read using single asynchronous mode or synchronous burst modereads. Status register data is output on DQ[7:0], while 0x00 is output on DQ[15:8]. Inasynchronous mode, the falling edge of OE# or CE# (whichever occurs first) updatesand latches the status register contents. However, when reading the status register insynchronous burst mode, CE# or ADV# must be toggled to update status data.

The device write status bit (SR7) provides the overall status of the device. SR[6:1]

present status and error information about the PROGRAM, ERASE, SUSPEND, VPP, andBLOCK LOCK operations.

Note: Reading the status register is a nonarray READ operation. When the operation oc-curs in asynchronous page mode, only the first data is valid and all subsequent data areundefined. When the operation occurs in synchronous burst mode, the same data wordrequested will be output on successive clock edges until the burst length requirementsare satisfied.

Table 16: Status Register Description

Notes apply to entire tableBitsName765:4Device write status(DWS)Erase Suspend Status(ESS)Erase/Blank check status(ES)Program status (PS)VPP status (VPPS)Program suspend status(PSS)Block lock status (BLS)BEFP status (BWS)Bit Settings0 = Busy1 = Ready0 = Not in effect1 = In effect00 = PROGRAM/ERASE successful01 = PROGRAM error10 = ERASE/BLANK CHECK error11 = Command sequence error0 = Within limits1 = Exceeded limits (VPP ≤ VPPLK)0 = Not in effect1 = In effect0 = Not locked1 = Locked (operation aborted)0 = BEFP complete1 = BEFP in progressDescriptionStatus bit: Indicates whether a PROGRAM orERASE command cycle is in progress.Status bit: Indicates whether an ERASE operationhas been or is going to be suspended.Status/Error bit: Indicates whether an ERASE/BLANK CHECK or PROGRAM operation was success-ful. When an error is returned, the operation isaborted.Status bit: Indicates whether a PROGRAM/ERASEoperation is within acceptable voltage range limits.Status bit: Indicates whether a PROGRAM opera-tion has been or is going to be suspended.Status bit: Indicates whether a block is lockedwhen a PROGRAM or ERASE operation is initiated.Status bit: Indicates whether BEFP data has com-pleted loading into the buffer.3210PDF: 09005aef84566799

p30_65nm_MLC_256Mb-512mb.pdf - Rev. C 12/13 EN

256Mb and 512Mb (256Mb/256Mb), P30-65nm

Configuration Register

Figure 14: Example Latency Count Setting Using Code 3

0CLK123tData4CE#ADV#A[MAX:1]Code 3D[15:0]High-ZAddressDataR103End of Wordline Considerations

End of wordline (EOWL) wait states can result when the starting address of the burst op-eration is not aligned to a 16-word boundary; that is, A[4:1] of the start address does notequal 0x0. The figure below illustrates the end of wordline wait state(s) that occur afterthe first 16-word boundary is reached. The number of data words and wait states issummarized in the table below.

Figure 15: End of Wordline Timing Diagram

Latency CountCLKA[MAX:1]

AddressDQ[15:0]ADV#OE#WAIT#

DataDataDataEOWLPDF: 09005aef84566799

p30_65nm_MLC_256Mb-512mb.pdf - Rev. C 12/13 EN

256Mb and 512Mb (256Mb/256Mb), P30-65nm

DC Electrical Specifications

Table 40: DC Current Characteristics (Continued)

CMOS Inputs(VCCQ = 1.7–3.6V)ParameterVPP blank checkSymbolIPPBCTyp0.050.05Max0.10.1TTL Inputs(VCCQ = 2.4–3.6V)Typ0.050.05Max0.10.1UnitTest ConditionsmAVPP = VPPLVPP = VPPHNotes3PDF: 09005aef84566799

p30_65nm_MLC_256Mb-512mb.pdf - Rev. C 12/13 EN

256Mb and 512Mb (256Mb/256Mb), P30-65nm

AC Read Specifications

Table 44: AC Read Specifications (Continued)

ParameterCLK frequencySymboltCLKMinEasy BGAQUAD+TSOPEasy BGAQUAD+TSOPEasy BGAQUAD+TSOP–Max5240UnitMHzNotes1, 3, 5, 6CLK periodtCLK19.225590.3999––ns1, 3, 5, 6CLK HIGH/LOW timetCH/CL–ns1, 3, 5, 6CLK fall/rise timeSynchronous Specifications5Address setup to CLKADV# LOW setup to CLKCE# LOW setup to CLKCLK to output validtFCLK/RCLK3–––1720nsns1, 3, 5, 61, 6tAVCH/LtVLCH/LtELCH/LtCHQV /tCLQVEasy BGAQUAD+TSOPtCHQXtCHAXns1, 6Output hold from CLKAddress hold from CLKCLK to WAIT validtCHTV310–--1720nsnsns1, 61, 4, 61, 6Easy BGAQUAD+TSOPtCHVLCLK valid to ADV# setupWAIT hold from CLKtCHTX335––nsns11, 6Easy BGAQUAD+TSOPNotes:

1.See AC Test Conditions for timing measurements and maximum allowable input slew

rate.

2.OE# may be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to

tELQV.

3.Sampled, not 100% tested.

4.Address hold in synchronous burst mode is tCHAX or tVHAX, whichever timing specifica-tion is satisfied first.

5.Synchronous read mode is not supported with TTL level inputs.6.Applies only to subsequent synchronous reads.

PDF: 09005aef84566799

p30_65nm_MLC_256Mb-512mb.pdf - Rev. C 12/13 EN

256Mb and 512Mb (256Mb/256Mb), P30-65nm

AC Read Specifications

Figure 30: Asynchronous Single-Word Read (ADV# LOW)