DS302 (v3.7) September 9, 2009
00Product Specification
Virtex-4 FPGA Electrical Characteristics
Virtex?-4 FPGAs are available in -12, -11, and -10 speedgrades, with -12 having the highest performance.
Virtex-4 FPGA DC and AC characteristics are specified forboth commercial and industrial grades. Except the operat-ing temperature range or unless otherwise noted, all the DCand AC electrical parameters are the same for a particularspeed grade (that is, the timing characteristics of a -10speed grade industrial device are the same as for a -10speed grade commercial device). However, only selectedspeed grades and/or devices might be available in theindustrial range.
All supply voltage and junction temperature specificationsare representative of worst-case conditions. The parame-ters included are common to popular designs and typicalapplications.
This Virtex-4 FPGA Data Sheet is part of an overall set ofdocumentation on the Virtex-4 family of FPGAs that is avail-able on the Xilinx website:?????????
Virtex-4 Family Overview, DS112Virtex-4 FPGA User Guide, UG070
Virtex-4 FPGA Configuration Guide, UG071
XtremeDSP for Virtex-4 FPGAs User Guide, UG073Virtex-4 FPGA Packaging and Pinout Specification,UG075
Virtex-4 FPGA PCB Designer’s Guide, UG072
Virtex-4 RocketIO? Multi-Gigabit Transceiver UserGuide, UG076
Virtex-4 FPGA Embedded Tri-Mode Ethernet MACUser Guide, UG074
PowerPC? 405 Processor Block Reference Guide,UG018
All specifications are subject to change without notice.
Virtex-4 FPGA DC Characteristics
Table 1: Absolute Maximum Ratings
Symbol
VCCINTVCCAUXVCCOVBATTVREF
Description
Internal supply voltage relative to GNDAuxiliary supply voltage relative to GNDOutput drivers supply voltage relative to GNDKey memory battery backup supplyInput reference voltage
I/O input voltage relative to GND (all user and dedicated I/Os)
–0.5 to 1.32–0.5 to 3.0–0.5 to 3.75–0.5 to 4.05–0.3 to 3.75–0.75 to 4.05–0.95 to 4.4
(Commercial Temperature)
Units
VVVVVV
VIN
I/O input voltage relative to GND
(restricted to maximum of 100 user I/Os)(3,4)2.5V or below I/O input voltage relative to GND (user and dedicated I/Os)
–0.85 to 4.3
(Industrial Temperature)
V
–0.75 to VCCO+0.5
±100±200
VmAmA
IIN
Current applied to an I/O pin, powered or unpoweredTotal current applied to all I/O pins, powered or unpowered
DS302 (v3.7) September 9, 2009Product Specification
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Speed Grade
Symbol
IDELAYCTRLTIDELAYCTRLCO_RDYFIDELAYCTRL_REF
IDELAYCTRL_REF_PRECISION(2)
Description
Reset to Ready for IDELAYCTRL (Maximum)REFCLK frequencyREFCLK precisionMinimum Reset pulse widthIDELAY Chain Delay ResolutionCumulative delay at a given tap(3)Pattern dependent period jitter in delay chain for clock pattern
Pattern dependent period jitter in delay chain for random data pattern (PRBS 23)C clock maximum frequency
-12-11-10Units
3.00200±1050.075
3.00200±1050.075
3.00200±1050.075
μs
MHzMHz
nspsps
TIDELAYCTRL_RPWIDELAY
TIDELAYRESOLUTIONTIDELAYTOTAL_ERR
[(tap?1)x75+34] ±0.07[(tap?1)x75+34]010±2300
010±2250
010±2250
Note (4) Note (4) MHz
TIDELAYPAT_JITFMAX
DS302 (v3.7) September 9, 2009Product Specification
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
CLB Switching Characteristics
Table 37: CLB Switching Characteristics
Speed Grade-12
Symbol
Combinatorial DelaysTILOTIF5TIF5XTIF6YTINAFXTINBFXTBXXTBYYTBXCYTBYCYTBYPTOPCYFTOPCYG
Sequential DelaysTCKOTCKLOTDICK/TCKDITCECK/TCKCETFXCK/TCKFXTSRCK/TCKSRTCINCK/TCKCINSet/ResetTRPWTRQFTOG
Minimum Pulse Width, SR/BY inputsDelay from SR/BY inputs to XQ/YQ outputs (asynchronous)
Toggle Frequency (MHz) (for export control)
0.541.051181
0.531.031205
0.591.151205(4)
0.701.351028
ns, Minns, MaxMHz
FF Clock CLK to XQ/YQ outputsLatch Clock CLK to XQ/YQ outputs
0.280.37
0.280.36
0.310.41
0.360.48
ns, Maxns, Max
4-input function: F/G inputs to X/Y outputs5-input function: F/G inputs to F5 output5-input function: F/G inputs to X outputFXINA or FXINB inputs to YMUX outputFXINA input to FX output via MUXFXFXINB input to FX output via MUXFXBX input to XMUX outputBY input to YMUX output
BX input to COUT output – Getting into carry chain(3)BY input to COUT output – Getting into carry chain(3)CIN input to COUT output – Carry chain delay(3)
F input to COUT output – Getting out from carry chain(3)G input to COUT output – Getting out from carry chain(3)
0.150.360.440.300.210.210.590.430.600.490.070.450.44
0.150.350.430.300.210.200.580.430.590.480.070.440.43
0.170.400.490.340.230.230.650.480.660.540.080.500.48
0.200.460.570.390.270.260.760.560.780.630.090.580.57
ns, Maxns, Maxns, Maxns, Maxns, Maxns, Maxns, Maxns, Maxns, Maxns, Maxns, Maxns, Maxns, Max
-11-10
Units
DescriptionXC4VFX(2)
XC4VLX/SXALL DEVICES
Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK
BX/BY inputsCE input
FXINA/FXINB inputsSR/BY inputs (synchronous)
CIN Data Inputs (DI) – Getting out from carry chain(3)
0.36–0.090.58–0.160.42–0.141.04–0.740.52–0.23
0.36–0.090.57–0.160.41–0.141.02–0.730.51–0.23
0.40–0.090.64–0.160.46–0.141.15–0.730.57–0.23
0.47–0.090.75–0.160.54–0.141.35–0.730.67–0.23
ns, Minns, Minns, Minns, Minns, Min
Notes:
1.A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case,” but if a “0” is listed,
there is no positive hold time.
2.The values in this column apply to all XC4VFX -12 parts except XC4VFX12 -12. For XC4VFX12 -12 values, use the values in the adjacent 4VLX/SX
-12 column.
3.These items are of interest for Carry Chain applications.4.XC4VFX -11 devices are 1181MHz.
DS302 (v3.7) September 9, 2009Product Specification
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 43: Configuration Switching Characteristics (Continued)
Speed Grade
Symbol
Boundary-Scan Port Timing SpecificationsTTAPTCKTTCKTAPTTCKTDOFTCKFTCKB
TMS and TDI Setup time before TCKTMS and TDI Hold time after TCKTCK falling edge to TDO output validMaximum configuration TCK clock frequency
Maximum Boundary-Scan TCK clock frequency
1.02.06.06650
1.02.06.06650
1.02.06.06650
ns, Minns, Minns, MaxMHz, MaxMHz, Max
Description-12-11-10Units
Dynamic Reconfiguration Port (DRP) for DCMCLKIN_FREQ_DLL_HF_MS_MAXTDMCCK_DADDR/TDMCKC_DADDRTDMCCK_DI/TDMCKC_DITDMCCK_DEN/TDMCKC_DENTDMCCK_DWE/TDMCKC_DWETDMCKO_DOTDMCKO_DRDY
Maximum frequency for DCLKDADDR Setup/Hold timeDI Setup/Hold timeDEN Setup/Hold timeDWE Setup/Hold timeCLK to out of DO(2)CLK to out of DRDY
5000.540.000.540.000.580.000.580.0000.68
4500.630.000.630.000.580.000.580.0000.80
4000.720.000.720.000.580.000.580.0000.92
MHz, Maxns, Maxns, Maxns, Maxns, Max ns,Max
ns, Max
DS302 (v3.7) September 9, 2009
Product Specification
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Clock Buffers and Networks
Table 44: Global Clock Switching Characteristics (Including BUFGCTRL)
Speed Grade
Symbol
TBCCCK_CE/TBCCKC_CE(1)TBCCCK_S/TBCCKC_S(1)TBCCKO_O
Maximum FrequencyFMAX
Global clock tree
500
450
400
MHz
CE pins Setup/HoldS pins Setup/HoldBUFGCTRL delay
Description-12
0.270.000.270.000.70
-11
0.310.000.310.000.77
-10
0.350.000.350.000.90
Units
nsnsns
DS302 (v3.7) September 9, 2009Product Specification
FPGA可编程逻辑器件芯片XC4VLX60-11FF1148C中文规格书 - 图文
