FPGA可编程逻辑器件芯片XC4VLX40-10FFG1148C中文规格书 - 图文

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DS302 (v3.7) September 9, 2009

00Product Specification

Virtex-4 FPGA Electrical Characteristics

Virtex?-4 FPGAs are available in -12, -11, and -10 speedgrades, with -12 having the highest performance.

Virtex-4 FPGA DC and AC characteristics are specified forboth commercial and industrial grades. Except the operat-ing temperature range or unless otherwise noted, all the DCand AC electrical parameters are the same for a particularspeed grade (that is, the timing characteristics of a -10speed grade industrial device are the same as for a -10speed grade commercial device). However, only selectedspeed grades and/or devices might be available in theindustrial range.

All supply voltage and junction temperature specificationsare representative of worst-case conditions. The parame-ters included are common to popular designs and typicalapplications.

This Virtex-4 FPGA Data Sheet is part of an overall set ofdocumentation on the Virtex-4 family of FPGAs that is avail-able on the Xilinx website:?????????

Virtex-4 Family Overview, DS112Virtex-4 FPGA User Guide, UG070

Virtex-4 FPGA Configuration Guide, UG071

XtremeDSP for Virtex-4 FPGAs User Guide, UG073Virtex-4 FPGA Packaging and Pinout Specification,UG075

Virtex-4 FPGA PCB Designer’s Guide, UG072

Virtex-4 RocketIO? Multi-Gigabit Transceiver UserGuide, UG076

Virtex-4 FPGA Embedded Tri-Mode Ethernet MACUser Guide, UG074

PowerPC? 405 Processor Block Reference Guide,UG018

All specifications are subject to change without notice.

Virtex-4 FPGA DC Characteristics

Table 1: Absolute Maximum Ratings

Symbol

VCCINTVCCAUXVCCOVBATTVREF

Description

Internal supply voltage relative to GNDAuxiliary supply voltage relative to GNDOutput drivers supply voltage relative to GNDKey memory battery backup supplyInput reference voltage

I/O input voltage relative to GND (all user and dedicated I/Os)

–0.5 to 1.32–0.5 to 3.0–0.5 to 3.75–0.5 to 4.05–0.3 to 3.75–0.75 to 4.05–0.95 to 4.4

(Commercial Temperature)

Units

VVVVVV

VIN

I/O input voltage relative to GND

(restricted to maximum of 100 user I/Os)(3,4)2.5V or below I/O input voltage relative to GND (user and dedicated I/Os)

–0.85 to 4.3

(Industrial Temperature)

–0.75 to VCCO+0.5

±100±200

VmAmA

IIN

Current applied to an I/O pin, powered or unpoweredTotal current applied to all I/O pins, powered or unpowered

DS302 (v3.7) September 9, 2009Product Specification

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

Interface Performance Characteristics

Table 13: Interface Performance

Speed Grade

Description

Networking ApplicationsSFI-4.1 (SDR LVDS Interface)(1)SPI-4.2 (DDR LVDS Interface)Memory Interfaces

DDR2 SDRAM (High-Performance SERDES Design)(2)DDR2 SDRAM (Low-Latency Direct Clocking Design)(3)QDRII SRAM (Low-Latency Direct Clocking Design)(4)DDR SDRAM (Low-Latency Direct Clocking Design)(5)RLDRAM II (Low-Latency Direct Clocking Design)(6)

600Mb/s420Mb/s550Mb/s344Mb/s470Mb/s

533Mb/s410Mb/s500Mb/s336Mb/s470Mb/s

500Mb/s400Mb/s400Mb/s330Mb/s400Mb/s

710MHz1Gb/s

645MHz800Mb/s

-12-11-10

DS302 (v3.7) September 9, 2009Product Specification

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

Since individual family members are produced at differenttimes, the migration from one category to another dependscompletely on the status of the fabrication process for eachdevice.

All specifications are always representative of worst-casesupply voltage and junction temperature conditions.

Testing of Switching Characteristics

All devices are 100% functionally tested. Internal timingparameters are derived from measuring internal test pat-terns. Listed below are representative values. For morespecific, more precise, and worst-case guaranteed data,

use the values reported by the static timing analyzer (TRCEin the Xilinx Development System) and back-annotate to thesimulation net list. Unless otherwise noted, values apply toall Virtex-4 devices.

PowerPC Switching Characteristics

Consult the PowerPC 405 Processor Block Reference Guide for further information.Table 15: PowerPC 405 Processor Clocks Absolute AC Characteristics

Speed Grade

-12

Description

Characteristics when APU Not Used

CPMC405CLOCK frequency(1,4)CPMDCRCLK(3)CPMFCMCLK(3)

JTAGC405TCK frequency(2)PLBCLK(3)

BRAMDSOCMCLK(3)BRAMISOCMCLK(3)

00NA0000

450450NA225450450450

00NA0000

400400NA200400400400

00NA0000

350350NA175350350350

MHzMHzMHzMHzMHzMHzMHz

-11

Max

Min

Max

Min

-10

Max

Units

Min

Characteristics when APU Used

CPMC405CLOCK frequency(1,4)CPMDCRCLK(3)CPMFCMCLK(3)

JTAGC405TCK frequency(2)PLBCLK(3)

BRAMDSOCMCLK(3)BRAMISOCMCLK(3)

0000000

333333333166.5333333333

0000000

275275275137.5275275275

0000000

233233233116.5233233233

MHzMHzMHzMHzMHzMHzMHz

Notes:

1.Worst-case DCM output clock jitter is included in these specifications.

2.The theoretical maximum frequency of this clock is one-half the CPMC405CLOCK. However, the achievable maximum is system dependent, and will

be much less.

3.The theoretical maximum frequency of these clocks is equal to the CPMC405CLOCK. Integer clock ratios are required for the CPMC405CLOCK and

BRAMDSOCMCLK, CPMC405CLOCK and BRAMISOCMCLK, CPMC405CLOCK and CPMDCRCLK, CPMC405CLOCK and CPMFCMCLK, andCPMC405CLOCK and PLBCLK. The integer ratios can be different for each interface. However, the achievable maximum is system dependent.4.Maximum operating frequency of CPMC405CLOCK is specified with the input pin TIEC405DISOPERANDFWD connected to a logic1.

DS302 (v3.7) September 9, 2009Product Specification

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

IOSTANDARD Attribute(1)

-12

HSTL_II_DCI(3)HSTL_III_DCI(3)HSTL_IV_DCI(3)HSTL_I_DCI_18(3)HSTL_II_DCI_18(3)HSTL_III_DCI_18(3)HSTL_IV_DCI_18(3)SSTL2_I_DCI(3)SSTL2_II_DCI(3)LVPECL_25SSTL18_ISSTL18_IISSTL18_I_DCI(3)SSTL18_II_DCI(3)

1.281.281.281.261.261.261.261.311.311.381.311.311.311.31

TIOPI

Speed Grade

TIOOP

Speed Grade

TIOTP

Speed Grade

Units

-10

2.132.222.032.212.162.092.062.462.451.742.542.242.322.18

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-11