Boundary-Scan and JTAG Configuration
Introduction
Virtex?-5 devices support IEEE standards 1149.1 and 1532. IEEE 1532 is a standard for In-System Configuration (ISC), based on the IEEE 1149.1 standard. JTAG is an acronym for the Joint Test Action Group, the technical subcommittee initially responsible for developing the standard. This standard provides a means to ensure the board-level integrity of individual components and the interconnections between them. The IEEE 1149.1 Test Access Port and Boundary-Scan Architecture is commonly referred to as JTAG. With multi-layer PC boards becoming increasingly dense and more sophisticated surface mounting techniques in use, Boundary-Scan testing is becoming widely used as an important debugging tool.
Devices containing Boundary-Scan logic can send data out on I/O pins in order to test connections between devices at the board level. The circuitry can also be used to send signals internally to test the device-specific behavior. These tests are commonly used to detect opens and shorts at both the board and device level.
In addition to testing, Boundary-Scan offers the flexibility for a device to have its own set of user-defined instructions. The added common vendor-specific instructions, such as configure and verify, have increased the popularity of Boundary-Scan testing and functionality.
JTAG Configuration/Readback
Full Initial Configuration or Reconfiguration
1.2.3.4.5.6.7.8.
Load the JPROGRAM instruction into the JTAG Instruction Register (IR).
Loop on an Instruction Register load/capture with the CFG_IN instruction and waitfor the captured value of INIT_COMPLETE (bit 4 of IR capture) to be 1.Go to Shift-DR and load the new bitstream.Go to the Test-Logic-Reset state (TLR).Load the JSTART instruction into the JTAG IR.Go to Run-Test-Idle (RTI).Clock TCK for 12 cycles.
Load the CFG_IN instruction into the JTAG IR.
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2020
Table 4-3:ICAP_VIRTEX5 Pin Table (Continued)Pin Name O[31:0]
TypeOutput
Description
Unregistered ICAP read data bus. The bus width depends on the ICAP_WIDTH parameter. The bit ordering is identical to the SelectMAP interface. See SelectMap Data Ordering in Figure2-19.
Active-High busy status. Only used in read operations. BUSY remains Low during writes.
BUSYOutput
FRAME_ECC_VIRTEX5
The Virtex-5 Frame error correction code (ECC) logic is designed to detect single- or double-bit errors in configuration frame data. It uses SECDED (Hamming code) parity values based on the frame data generated by BitGen. During readback, the Frame ECC logic calculates a syndrome value using all the bits in the frame, including the ECC bits. If the bits have not changed from the original programmed values, then the syndrome bits are all 0s. If a single bit has changed, including any of the ECC bits, then the location of the bit is indicated by syndrome bits 10:0 and the syndrome bit 11 is 1. If two bits have
changed, then syndrome bit 11 is 0 and the remaining bits are non-zero and meaningless. If more than two bits have changed, then the syndrome bits is indeterminate. The error output of the block is asserted if one or two bits have changed, indicating that action needs to be taken.
To use the Frame ECC logic, FRAME_ECC_VIRTEX5 must be instantiated in the user's design, and readback must be performed through SelectMAP, JTAG, or ICAP. At the end of each frame of readback, the syndrome_valid signal is asserted for one cycle of the readback clock (CCLK, TCK, or ICAP_CLK). The number of cycles required to read back a frame varies with the interface used. Refer to “Readback and Configuration Verification” in Chapter7 for further information.
The FRAME_ECC_VIRTEX5 logic does not repair changed bits; this requires a user design. The design must be able to store at least one frame of data, or be able to fetch original frames of data for reload. A single frame is 1,312 bits. Following is an example of a simple repair implementation:1.2.
A frame is read out through ICAP and stored in block RAM. The frame address mustbe generated as each frame is read.
If an error is indicated by the error output of the FRAME_ECC block, then the readback is halted and the syndrome value is saved. If bit 11 is 0, then the whole frame must berestored. If bit 11 is 1, then bits 10:0 are used to locate the error bit in the saved frame,and the bit is inverted.
The repaired frame is then written back into the frame address generated in step 1.Readback then begins again with the next frame address.
3.4.
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2020
Boundary-Scan for Virtex-5 Devices Using IEEE Standard 1149.1
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2020
Chapter 3:Boundary-Scan and JTAG Configuration
Boundary-Scan for Virtex-5 Devices Using IEEE Standard 1532
ISC Modal States
Any non-test instruction,but ISC_ENABLEexecutedISC_ENABLE is executedUnprogrammed(0,0)TLR & ISC_Done is clearISC_Accessed(1,X)Any non-testinstruction, butISC_DISABLEexecutedAny non-test instruction, but ISC_DISABLE loaded and ISC_DONE is clearISC_Done is clearPowerUP TLR and ISC_Doneis setISC_ENABLEexecutedISC_DISABLEexecutedISC_Done is setAny non-test instruction,but ISC_ENABLEexecutedISC_DISABLEloadedOperational(0,1)Any non-test instruction, but ISC_DISABLE loadedand ISC_DONE is setISC Complete(0,X)(ISC_Enabled, ISC_Done)UG191_c3_08_050406
Figure 3-8:ISC Modal States
Once the device is powered up, it goes to the Unprogrammed state. The I/Os are all either 3-stated or pulled up. When ISC_ENABLE is successfully executed, the ISC_Enabled
signal is asserted, and the device moves to the ISC_Accessed state. When the device movesto the ISC_Accessed state from the Operational state, the shutdown sequence is executed.The I/Os are all either 3-stated or pulled up.
The startup sequence is executed when in the ISC_Accessed state. At the end of the startup sequence, ISC_Enabled is cleared and the device moves to ISC_Complete. The minimum clock cycle requirement is the number of clock cycles required to complete the startup sequence. At the completion of the minimum required clock cycles, ISC_Enabled is deasserted.
Whether the startup sequence is successful or not is determined by CRC or configuration error status from the configuration processor. If the startup is completed, ISC_Done is asserted; otherwise, ISC_Done stays Low. The I/Os are either 3-stated or pulled up.When ISC_Done is set in ISC_Complete state, the device moves to the Operational state. Otherwise, if ISC_Done is clear, the device moves to the Unprogrammed state. However, if the TAP controller goes to the TLR state while the device is in ISC_Accessed state, and if ISC_Done is set, then the device moves to the Operational state.
Though Operational, the I/O is not active yet because the startup sequence has not been performed. The startup sequence has to be performed in the Operational state to bring the I/O active.
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2020
Chapter 4:User Primitives
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2020
FPGA可编程逻辑器件芯片XC2S384-7FT256C中文规格书 - 图文
