Chapter 1:StratixIII Device Data Sheet: DC and Switching CharacteristicsElectrical Characteristics
Refer to the figures for “Differential I/O Standards” in “Glossary” for receiver input and transmitter output waveforms, and for all differential I/O standards (LVDS, mini-LVDS, RSDS). VCC_CLKIN is the power supply for differential column clock input pins. VCCPD is the power supply for row I/Os and all other column I/Os.
Table1–16.Differential SSTL I/O Standard Specifications I/O Standard
SSTL-2 CLASSI,IISSTL-18 CLASSI,IISSTL-15 CLASSI,II
VCCIO (V)Min2.3751.711.425
Typ2.51.81.5
Max2.6251.891.575
VSWING (DC) (V)Min0.30.250.2
Max
VCCIO
VX (AC) (V)Min
VCCIO/2
VSWING(AC) (V)
Max
VCCIO/2
VOX (AC) (V)Min
VCCIO/2
Typ——
VCCIO/2
Min0.620.50.35
Max
VCCIO
Typ——
VCCIO/2
Max
VCCIO/2 + 0.15VCCIO/2 +0.125
+0.6
VCCIO
-0.2
VCCIO/2
+0.2
VCCIO/2
+0.6
VCCIO
-0.15
VCCIO/2
+0.6—
-0.175—
+0.175—
+0.6—
-0.125—
—
Table1–17. Differential HSTL I/O Standards SpecificationsI/O Standard
HSTL-18 CLASSI,IIHSTL-15 CLASSI,IIHSTL-12 CLASSI,II
VCCIO (V)Min1.711.4251.14
Typ1.81.51.2
Max1.891.5751.26
VDIF(DC) (V)Min0.20.20.16
Max——
VCCIO
VX(AC) (V)Min0.780.68—
Typ——
0.5* VCCIO
VCM(DC) (V)
Max1.120.9—
Min0.780.68
0.4* VCCIO
VDIF(AC) (V)
Max1.120.9
0.6* VCCIO
Typ——
0.5* VCCIO
Min0.40.40.3
Max——
VCCIO
+0.3+0.48
Table1–18.Differential I/O Standard Specifications (Part 1 of 2)I/O Standard
VCCIO (V)Min2.3752.3752.3752.3752.3752.3752.3752.375
Typ2.52.52.52.52.52.52.52.5
Max2.6252.6252.6252.6252.6252.6252.625
Min0.10.10.10.10.10.10.2
VID (V)(1)Condition
VCM = 1.25VCM = 1.25VCM = 1.25VCM = 1.25VCM = 1.25VCM = 1.25
VICM(DC) (V)
Max——————0.60.6
Min0.05 (6)1.05 (6)0.05 (6)
1.05
VOD (V) (2)
Max1.8 (6)
1.55
VOCM (V) (2)
Max0.60.60.60.60.60.60.60.6
Min
Typ
Max
ConditionDmax?? 700
Mbps
Min0.2470.2470.2470.2470.10.10.250.25
Typ————0.20.2——
2.5V LVDS (Row I/O)
1.1251.251.3751.1251.251.3751.01.00.50.50.50.5
1.251.251.21.21.21.2
1.51.51.41.51.41.5
Dmax >700
Mbps
(6)
1.8
Dmax?? 700
Mbps
2.5V LVDS (Column I/O)RSDS (Row I/O)RSDS
(Column I/O)Mini-LVDS (Row I/O)Mini-LVDS (Column I/0)
(6)1.55 (6)1.41.41.3251.325
Dmax >700
Mbps
(6)0.30.30.40.4
————
——
2.625 0.2Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics
Switching Characteristics
Table1–18.Differential I/O Standard Specifications (Part 2 of 2)I/O Standard
VCCIO (V)Min
Typ
Max
Min0.30.3
VID (V)(1)Condition——
Max——
Min0.61.0
VICM(DC) (V)ConditionDmax?? 700
Mbps
VOD (V) (2)
Max1.8 (4)1.6(4)
Min——
Typ——
Max——
Min——
VOCM (V) (2)Typ——
Max——
LVPECL(3)
2.375 2.5 2.625(5)(5)(5)2.375(5)
2.5(5)
2.625(5)
Dmax >700
Mbps
Notes to Table1–18:
(1)The minimum VID value is applicable over the entire common mode range, VCM.(2)RL range: 90 ??RL ? 110?.
(3)Column and row I/O banks support LVPECL I/O standards for input operation only on dedicated clock input pins. Differential clock inputs in column I/O use
VCC_CLKIN which should be powered by 2.5 V. Differential clock inputs in row I/O are powered by VCCPD.(4)The receiver voltage input range for data rate when Dmax > 700Mbps,0.85V ??VIN ??1.75V.
The receiver voltage input range for data rate when Dmax ??700Mbps, 0.45V ??VIN ??1.95V(5)Power supply for column I/O LVPECL differential clock input buffer is VCC_CLKIN.
(6)The receiver voltage input range for data rate when Dmax > 700Mbps, 1.0V ??VIN ??1.6V.
The receiver voltage input range for data rate when Dmax ??700Mbps, zeroV ??VIN ??1.85V.
Power Consumption
Altera offers two ways to estimate power for a design: the Excel-based Early Power Estimator and the Quartus?II PowerPlay Power Analyzer feature.
The interactive Excel-based Early Power Estimator is typically used prior to designing the FPGA in order to get a magnitude estimate of the device power. The QuartusII PowerPlay Power Analyzer provides better quality estimates based on the specifics of the design after the place-and-route is complete. The PowerPlay Power Analyzer can apply a combination of user-entered, simulation-derived and estimated signal activities which, combined with detailed circuit models, can yield very accurate power estimates.
See Table1–4 for supply current estimates for VCCPGM and VCC_CLKIN. Use the EPE and PowerPlay Power Analyzer for current estimates of remaining power supplies.
f
For more information about power estimation tools, refer to the PowerPlay Early Power Estimator User Guide For StratixIII FPGAs and the PowerPlay Power Analysis chapter in the QuartusII Handbook.
Switching Characteristics
This section provides performance characteristics of StratixIII core and periphery blocks for commercial grade devices.
These characteristics can be designated as Preliminary and Final and each designation is defined below. Preliminary
Preliminary characteristics are created using simulation results, process data, and other known parameters. Final
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics
I/O Timing
Figure1–5.Output Register Clock to Output Timing Diagram
DatainClockClock pad to output Register delayOutput Register micro tCOOutput Register to output pin delayOutputSimulation using IBIS models is required to determine the delays on the PCB traces in addition to the output pin delay timing reported by the QuartusII software and the timing model in the device handbook.
1.Simulate the output driver of choice into the generalized test setup, using values
from Table1–39.2.Record the time to VMEAS at the far end of the PCB trace.
3.Simulate the output driver of choice into the actual PCB trace and load, using the
appropriate IBIS model or capacitance value to represent the load.4.Record the time to VMEAS at the far end of the PCB trace.
5.Compare the results of steps 2 and 4. The increase or decrease in delay should be
added to or subtracted from the I/O Standard Output Adder delays to yield theactual worst-case propagation delay (clock-to-output) of the PCB trace.The QuartusII software reports the timing with the conditions shown in Table1–39 using the above equation. Figure1–6 shows the model of the circuit that is represented by the output timing of the QuartusII software.
Figure1–6.Output Delay Timing Reporting Setup Modeled by QuartusII Software for Single-Ended Outputs and Dedicated Differential Outputs (Note1)
VCCIOVTTOutputpRDRTOutputBufferOutputRSCLGNDVMEASOutputnGNDNote to Figure1–6:
(1)Output pin timing is reported at the output pin of the FPGA device. Additional delays for loading and board trace delay
need to be accounted for with IBIS model simulations.
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics
I/O Timing
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching CharacteristicsI/O Timing
Stratix III Device Handbook, Volume 2
FPGA可编程逻辑器件芯片EP2SGX30DF780C4N中文规格书 - 图文
