DC Characteristics
This section lists the input pin capacitances, on-chip termination tolerance, and hot- socketing specifications.Supply Current
Standby current is the current the device draws after the device is configured with no inputs/outputs toggling and no activity in the device. Since these currents vary largely with the resources used, use the Excel-based Early Power Estimator (EPE) to get supply current estimates for your design.
Table1–4 lists supply current specifications for VCC_CLKIN and VCCPGM. Use the EPE to get supply current estimates for remaining power supplies.Table1–4.Supply Current Specifications for VCC_CLKIN and VCCPGM
SymbolICLKINIPGM
Parameter
VCC_CLKIN current specificationsVCCPGM current specifications
Min00
Max250250
UnitmAmA
I/O Pin Leakage Current
Table1–5 defines StratixIII I/O Pin leakage current specifications.Table1–5.StratixIII I/O Pin Leakage Current (Note1), (2)SymbolIIIOZ
Parameter
Input Pin Leakage CurrentTri-stated I/O Pin Leakage Current
ConditionsVI = VCCIOMAX to 0 VVO = VCCIOMAX to 0 V
Min-10-10
Typ——
Max1010
Unit?A?A
Notes to Table1–5:
(1)This value is specified for normal device operation. The value may vary during power-up. This applies for all VCCIO
settings (3.3, 3.0, 2.5, 1.8, 1.5, and 1.2 V).(2)10-?A I/O leakage current limit is applicable when the internal clamping diode is off. A higher current can be
observed when the diode is on.
Bus Hold Specifications
Table1–7 shows the StratixIII device family bus hold specifications.
Table1–6.Bus Hold Parameters(Part 1 of 2)
VCCIO
Parameter
Symbol
Conditions
1.2VMin
Low sustaining currentHigh sustaining currentLow overdrive current
ISUSLISUSHIODL
VIN>VIL (maximum)VIN Max 1.5VMin Max 1.8VMin Max 2.5VMin Max 3.0V/3.3VMin Max μAμAμAUnit 22.5 —-22.5 —— 120 25.0 —-25.0 —— 160 30.0 —-30.0 —— 200 50.0 —-50.0 —— 300 70.0 —-70.0 —— 500 Stratix III Device Handbook, Volume 2 Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics Switching Characteristics DLL and DQS Logic Block Specifications Table1–32 describes the DLL frequency range specifications for StratixIII devices. Table1–32.StratixIII DLL Frequency Range SpecificationsFrequency Mode 01234567 Frequency Range (MHz) C2 90 – 150120 – 200150 – 240180 – 300240 – 370290 – 450360 – 560470 – 740 C3, I390 – 140120 – 190150 – 230180 – 290240 – 350290 – 420360 – 530470 – 700 C4, I490 – 120120 – 170150 – 200180 – 250240 – 310290 – 370360 – 460470 – 610 C4L, I4L90 – 120120 – 170150 – 200180 – 250240 – 310290 – 370360 – 460470 – 610 Available Phase Shift22.5°, 45°, 67.5°, 90°30°, 60°, 90°, 120°36°, 72°, 108°, 144°45°, 90°,135°, 180°30°, 60°, 90°,120°36°, 72°, 108°, 144°45°, 90°, 135°, 180°60°, 120°, 180°, 240° Number of Delay Chains 1612108121086 DQS Delay Buffer Mode (1) LowLowLowLowHighHighHighHigh Note to Table1–32: (1)Low indicates 6-bit DQS delay setting, high indicates 5-bit DQS delay setting. Table1–33 describes the average DQS phase offset delay per setting for StratixIII devices. Table1–33.Average DQS Phase Offset Delay per Setting (Note1), (2), (3)Speed Grade C2C3, I3C4, I4C4L, I4L Notes to Table1–33: (1)The valid settings for phase offset are -64 to +63 for frequency modes 0 to 3 and -32 to +31 for frequency modes 4 to 6.(2)The typical value equals the average of the minimum and maximum values. (3)The delay settings are linear with a cumulative delay variation of ±20ps for all speed grades. For example, when using a C2 speed grade and applying 10° phase offset settings to a 90° phase shift at 400 MHz, the expected minimum cumulative delay is [625 ps + (10*7 ps) - 20 ps] = 675 ps. Min7777 Typ101111.511.5 Max13151616 Unitpspspsps Table1–34.StratixIII DQS Phase Shift Error Specification for DLL-Delayed Clock (tDQS_PSERR) (Note1)Number of DQS Delay Buffer 1234 Note to Table1–34: (1)This error specification is the absolute maximum and minimum error. For example, skew on 3 DQS delay buffer in a C2 speed grade is ±39ps. C2±13±26±39±52 C3, I3 ±14±28±42±56 C4, C4L, I4, I4L ±15±30±45±60 Unitpspspsps Stratix III Device Handbook, Volume 2 Chapter 1:StratixIII Device Data Sheet: DC and Switching CharacteristicsSwitching Characteristics Stratix III Device Handbook, Volume 2 Chapter 1:StratixIII Device Data Sheet: DC and Switching CharacteristicsI/O Timing Table1–39.Output Timing Measurement Methodology for Output Pins(Part 3 of 3) I/O Standard RS MINI-LVDS_E_1RMINI-LVDS_E_3RRSDS_E_1RRSDS_E_3R Notes to Table1–39: (1)Hyper transport is not supported by StratixIII.(2)LVPECL outputs are not supported by StratixIII. (3)Quartus timing conditions can be changed using the Advanced I/O Timing feature.(4)VCC is nominally 1.1 V less 50 mV (1.05 V). (5)Terminated I/O standards require an additional 30 mV IR drop on VCC (1.02 V).(6)Terminated I/O standards required an additional 50 mV IR drop on VCCIO and VCCPD. Loading and Terminations RD100100100100 RT———— RP120170120170 VCCIO2.3252.3252.3252.325 VCCPD2.3252.3252.3252.325 VCC1.021.021.021.02 VTT———— CL (pF)0000 Measurement PointVMEAS (v)1.16251.16251.16251.1625 —120—120 I/O Default Capacitive Loading See Table1–40 for default capacitive loading of different I/O standards.Table1–40.Default Loading of Different I/O Standards for StratixIII (Part 1 of 2) I/O Standard 3.3-V LVTTL3.3-V LVCMOS3.0-V LVTTL3.0-V LVCMOS2.5-V LVTTL/LVCMOS1.8-V LVTTL/LVCMOS1.5-V LVTTL/LVCMOS3.0-V PCI3.0-V PCI-XSSTL-2 CLASSISSTL-2 CLASSIISSTL-18 CLASSISSTL-18 CLASSII1.5-V HSTL CLASSI1.5-V HSTL CLASSII1.8-V HSTL CLASSI1.8-V HSTL CLASSII1.2-V HSTL Differential SSTL-2 CLASSIDifferential SSTL-2 CLASSIIDifferential SSTL-18 CLASSI Capacitive Load 00000001010000000000000 UnitpFpFpFpFpFpFpFpFpFpFpFpFpFpFpFpFpFpFpFpFpF Stratix III Device Handbook, Volume 2 Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics I/O Timing Stratix III Device Handbook, Volume 2
FPGA可编程逻辑器件芯片EP1S60F1508I6中文规格书 - 图文
