Table 19: WAIT Functionality Table (Continued)
ConditionAll WritesNotes:
WAITHigh-Z1.Active means that WAIT is asserted until data becomes valid, then deasserts.2.When OE# = VIH during writes, WAIT = High-Z.
Notes1, 2WAIT Delay
The WAIT delay (WD) bit controls the WAIT assertion delay behavior during synchro-nous burst reads. WAIT can be asserted either during or one data cycle before valid datais output on DQ[15:0]. When WD is set, WAIT is de-asserted one data cycle before validdata (default). When WD is cleared, WAIT is de-asserted during valid data.
Burst Sequence
The burst sequence (BS) bit selects linear burst sequence (default). Only linear burst se-quence is supported. The synchronous burst sequence for all burst lengths, as well asthe effect of the burst wrap (BW) setting are shown below.
Table 20: Burst Sequence Word Ordering
Burst Addressing Sequence (DEC)StartAddress(DEC)01234567?1415?0123BurstWrap(RCR3)00000000?00?1111?0-1-2-31-2-3-42-3-4-53-4-5-6?0-1-2-3-4-5-6-71-2-3-4-5-6-7-82-3-4-5-6-7-8-93-4-5-6-7-8-9-10?4-Word Burst(BL[2:0] =0b001)0-1-2-31-2-3-02-3-0-13-0-1-28-Word Burst(BL[2:0] = 0b010)0-1-2-3-4-5-6-71-2-3-4-5-6-7-02-3-4-5-6-7-0-13-4-5-6-7-0-1-24-5-6-7-0-1-2-35-6-7-0-1-2-3-46-7-0-1-2-3-4-57-0-1-2-3-4-5-6?16-Word Burst(BL[2:0] = 0b011)0-1-2-3-4…14-151-2-3-4-5…15-02-3-4-5-6…15-0-13-4-5-6-7…15-0-1-24-5-6-7-8…15-0-1-2-35-6-7-8-9…15-0-1-2-3-46-7-8-9-10…15-0-1-2-3-4-57-8-9-10…15-0-1-2-3-4-5-6?14-15-0-1-2…12-1315-0-1-2-3…13-14?0-1-2-3-4…14-151-2-3-4-5…15-162-3-4-5-6…16-173-4-5-6-7…17-18Continuous Burst(BL[2:0] = 0b111)0-1-2-3-4-5-6-…1-2-3-4-5-6-7-…2-3-4-5-6-7-8-…3-4-5-6-7-8-9-…4-5-6-7-8-9-10…5-6-7-8-9-10-11…6-7-8-9-10-11-12-…7-8-9-10-11-12-13…?14-15-16-17-18-19-20-…15-16-17-18-19-20-21-…?0-1-2-3-4-5-6-…1-2-3-4-5-6-7-…2-3-4-5-6-7-8-…3-4-5-6-7-8-9-…PDF: 09005aef84566799
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Common Flash Interface
Table 27: Primary Vendor-Specific Extended Query (Continued)
Hex OffsetP = 10Ah(P+A)h(P+B)hLength2DescriptionBlock Status Register mask:Bits 2 - 15 are reserved; undefined bits are 0.Bit 0: Block lock-bit status register active.Bit 1: Block lock-down bit status active.Bit 4: EFA block lock-bit status register active.Bit 5: EFA block lock-bit status active.(P+C)h1VCC logic supply highest performance program/erase voltage.bits 0 - 3 BCD 100 mVbits 4 - 7 hex value in voltsVPP optimum program/erase voltage.bits 0 - 3 BCD 100mVbits 4 - 7 hex value in volts1.See Optional Features Fields table.
116:Address114:115:bit 0 = 1bit 1 = 1bit 4 = 0bit 5 = 0- -18Hex Code- -03- -00ASCII Value(DQ[7:0])––YesYesNoNo1.8V(P+D)h1117:- -909.0VNote:
Table 28: Optional Features Field
DiscreteAddress112:Bottom–--00Top–--00die 1 (B)40:Bottomdie 2 (T)--00die 1 (T)--40512MbTopdie 2 (B)--00Table 29: One Time Programmable (OTP) Space Information
Hex OffsetP = 10Ah(P+E)hLength1DescriptionNumber of OTP block fields in JEDEC ID space.00h indicates that 256 OTP fields are available.Address118:HexCode- -02ASCII Value(DQ[7:0])2PDF: 09005aef84566799
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Common Flash Interface
Table 29: One Time Programmable (OTP) Space Information (Continued)
Hex OffsetP = 10AhLengthDescriptionOTP Field 1: OTP Description:This field describes user-available OTP bytes.Some are preprogrammed with device-unique se-rial numbers. Others are user-programmable.Bits 0-15 point to the OTP Lock byte (the firstbyte).The following bytes are factory preprogrammedand user-programmable:Bits 0 - 7 = Lock/bytes JEDEC plane physical lowaddress.Bits 8 - 15 = Lock/bytes JEDEC plane physical highaddress.Bits 16 - 23 = n where 2n equals factory preprog-rammed bytes.Bits 24 - 31 = n where 2n equals user-programma-ble bytes.Protection field 2: protection descriptionBits 0 - 31 point to the protection register physi-cal lock word address in the JEDEC plane.The bytes that follow are factory or user-progam-mable.Bits 32 - 39 = n where n equals factory program-med groups (low byte).Bits 40 - 47 = n where n equals factory program-med groups (high byte).Bits 48 - 55 = n where 2n equals factory program-med bytes/groups.Bits 56 - 63 = n where n equals user programmedgroups (low byte).Bits 64 - 71 = n where n equals user programmedgroups (high byte).Bits 72 - 79 = n where 2n equals user programma-ble bytes/groups.Address119:11A:1B:11C:HexCode- -80- -00- -03- -03ASCII Value(DQ[7:0])80h00h8 byte8 byte(P+F)h(P+10)h(P+11)h(P+12)h4(P+13)h(P+14)h(P+15)h(P+16)h(P+17)h(P+18)h(P+19)h1011D:11E:11F:120:121:122:123:- -89- -00- -00- -00- -00- -00- -0089h00h00h00h000(P+1A)h(P+1B)h(P+1C)h124:125:126:- -10- -00- -0416016Table 30: Burst Read Information
Hex OffsetP = 10AhLength1(P+1D)hDescriptionPage Mode Read capability:Bits 7 - 0 = n where 2n hex value represents thenumber of read-page bytes. See offset 28h fordevice word width to determine page-mode dataoutput width. 00h indicates no read page buffer.Address127:HexCode- -05ASCII Value(DQ[7:0])32 bytePDF: 09005aef84566799
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DC Electrical Specifications
CMOS Inputs(VCCQ = 1.7–3.6V)ParameterInput low voltageInput high voltageOutput low voltageSymbolVILVIHVOLMin–0.5VCCQ - 0.4–Max0.4VCCQ + 0.50.2TTL Inputs1(VCCQ = 2.4–3.6V)Min–0.52–Max0.6VCCQ + 0.50.2UnitTest ConditionsVVVVCC = VCC (MIN)VCCQ = VCCQ (MIN)IOL = 100μAVCC = VCC (MIN)VCCQ = VCCQ (MIN)IOH = –100μA3Notes2Output high voltageVOHVCCQ - 0.2–VCCQ – 0.2–VVPP lock out voltageVCC lock voltageVCCQ lock voltageVPPLKVLKOVLKOQNotes:
–1.50.90.4–––1.50.90.4––VVV1.Synchronous read mode is not supported with TTL inputs.
2.VIL can undershoot to –1.0V for durations of 2ns or less and VIH can overshoot to VCCQ +
1.0V for durations of 2ns or less.
3.VPP ≤ VPPLK inhibits ERASE and PROGRAM operations. Do not use VPPL and VPPH outsidetheir valid ranges.
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AC Test Conditions and Capacitance
AC Test Conditions and Capacitance
Figure 27: AC Input/Output Reference Timing
VCCQ
Input VCCQ/20VTest pointsVCCQ/2 outputNote:
1.AC test inputs are driven at VCCQ for logic 1 and at 0V for logic 0. Input/output timing
begins/ends at VCCQ/2. Input rise and fall times (10% to 90%) <5ns. Worst-case speed oc-curs at VCC = VCC (MIN).
Figure 28: Transient Equivalent Load Circuit
Device undertest CLNotes:
Out
1.See the Test Configuration for Worst-Case Speed Conditions table for component values.2.CL includes jig capacitance.
Table 42: Test Configuration: Worst-Case Speed Condition
Test ConfigurationVCCQ(MIN) standard testCL (pF)30Figure 29: Clock Input AC Waveform
tCLKCLK
VIHVILtCH/CLtFCLK/RCLKPDF: 09005aef84566799
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MEMORY存储芯片MT40A512M8HX-093EA中文规格书 - 图文
