Power Consumption
Power
Consumption
Altera? offers two ways to calculate power for a design: the Excel-based PowerPlay Early Power Estimator power calculator and the Quartus?II PowerPlay Power Analyzer feature.
The interactive Excel-based PowerPlay Early Power Estimator is typically used prior to designing the FPGA in order to get an estimate of device power. The QuartusII PowerPlay Power Analyzer provides better quality estimates based on the specifics of the design after place-and-route is complete. The Power Analyzer can apply a combination of user-entered, simulation-derived and estimated signal activities which, combined with detailed circuit models, can yield very accurate power estimates.
In both cases, these calculations should only be used as an estimation of power, not as a specification.
f
For more information about PowerPlay tools, refer to the PowerPlay Early Power Estimator User Guide and the PowerPlay Early Power Estimator and PowerPlay Power Analyzer chapters in volume 3 of the QuartusII Handbook.
The PowerPlay Early Power Estimator is available on the Altera web site at www.altera.com. See Table5–4 on page5–3 for typical ICC standby specifications.
Timing Model
The DirectDriveTM technology and MultiTrackTM interconnect ensure predictable performance, accurate simulation, and accurate timing analysis across all StratixII device densities and speed grades. This
section describes and specifies the performance, internal timing, external timing, and PLL, high-speed I/O, external memory interface, and JTAG timing specifications.
All specifications are representative of worst-case supply voltage and junction temperature conditions.1
The timing numbers listed in the tables of this section are extracted from the QuartusII software version 5.0 SP1.
Preliminary & Final Timing
Timing models can have either preliminary or final status. The QuartusII software issues an informational message during the design compilation if the timing models are preliminary. Table5–33 shows the status of the StratixII device timing models.
Stratix II Device Handbook, Volume 1
Timing Model
Figure5–6.Measurement Setup for tzx
tZX, Tristate to Driving High DisableOEDoutOEEnable? VCCINTDin1 MΩDin“1”Douttzh? VCCIOtZX, Tristate to Driving Low DisableOE1 MΩOEDoutDintzl“0”? VCCIOEnable? VCCINTDinDoutTable5–35 specifies the input timing measurement setup.
Table5–35.Timing Measurement Methodology for Input Pins(Part 1 of2)
I/O Standard
LVTTL (5)LVCMOS (5)2.5 V (5)1.8 V (5)1.5 V (5)PCI (6)PCI-X (6)SSTL-2 Class ISSTL-2 Class IISSTL-18 Class ISSTL-18 Class II1.8-V HSTL Class I
Notes(1)–(4)
Measurement Point
VMEAS (V)
1.56751.56751.18750.8550.71251.4851.4851.16251.16250.830.830.83
Measurement ConditionsVCCIO (V)
3.1353.1352.3751.7101.4252.9702.9702.3252.3251.6601.6601.660
1.1631.1630.8300.8300.830
VREF (V)Edge Rate (ns)
3.1353.1352.3751.7101.4252.9702.9702.3252.3251.6601.6601.660
Stratix II Device Handbook, Volume 1
Document Revision History
Stratix II Device Handbook, Volume 1
Document Revision History
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Table5–35.Timing Measurement Methodology for Input Pins(Part 2 of2)
I/O Standard
1.8-V HSTL Class II1.5-V HSTL Class I1.5-V HSTL Class II1.2-V HSTL with OCTDifferential SSTL-2 Class IDifferential SSTL-2 Class IIDifferential SSTL-18 Class IDifferential SSTL-18 Class II1.5-V Differential HSTL Class I1.5-V Differential HSTL Class II1.8-V Differential HSTL Class I1.8-V Differential HSTL Class IILVDS
HyperTransportLVPECL
Notes to Table5–35:(1)(2)(3)(4)(5)(6)
Notes(1)–(4)
Measurement Point
VMEAS (V)
0.830.68750.68750.5701.16251.16250.830.830.68750.68750.830.831.16251.16251.5675
Measurement ConditionsVCCIO (V)
1.6601.3751.3751.1402.3252.3251.6601.6601.3751.3751.6601.6602.3252.3253.135
VREF (V)
0.8300.6880.6880.5701.1631.1630.8300.8300.6880.6880.8300.830
Edge Rate (ns)
1.6601.3751.3751.1402.3252.3251.6601.6601.3751.3751.6601.6600.1000.4000.100
Input buffer sees no load at buffer input.
Input measuring point at buffer input is 0.5 × VCCIO.Output measuring point is 0.5 × VCC at internal node.Input edge rate is 1 V/ns.
Less than 50-mV ripple on VCCIO and VCCPD, VCCINT = 1.15 V with less than 30-mV rippleVCCPD = 2.97 V, less than 50-mV ripple on VCCIO and VCCPD, VCCINT = 1.15 V
Performance
Table5–36 shows StratixII performance for some common designs. All performance values were obtained with the QuartusII software
compilation of library of parameterized modules (LPM), or MegaCore? functions for the finite impulse response (FIR) and fast Fourier transform (FFT) designs.
Stratix II Device Handbook, Volume 1
FPGA可编程逻辑器件芯片EP2SGX60DF780C4N中文规格书 - 图文
