1
Dedicated SERDES and DPA circuitry are only available on the right side of the device in row I/O banks. SERDES with DPA receivers are only available on differential pins in the row I/O banks and SERDES transmitters are only available on transmit (Tx) pins in the row I/O banks. The receive (Rx) pins in row I/O banks are receiver channels without dedicated SERDES and DPA circuitry.
Table8–1.LVDS Channels Supported in Arria II GX Device Row I/O Banks (Note1), (2), (3), (4), (5), (6)
DeviceEP2AGX45EP2AGX65EP2AGX95EP2AGX125EP2AGX190EP2AGX260
Notes to Table8–1:
(1)Dedicated SERDES and DPA circuitry only exist on the right side of the device in the Row I/O banks.
(2)RD = True LVDS input buffers with RD OCT support and dedicated SERDES receiver channel with DPA circuitry.(3)Rx = True LVDS input buffers without RD OCT support and dedicated SERDES receiver channel with DPA circuitry.(4)Tx = True LVDS output buffers and dedicated SERDES transmitter channel.(5)eTx = Emulated LVDS output buffers, either LVDS_E_3R or LVDS_E_1R.
(6)The LVDS channel count does not include dedicated clock input pins and PLL clock output pins.
358-Pin FlipChip UBGA8(RD or eTx) + 8(Rx, Tx or eTx)8(RD or eTx) + 8(Rx, Tx, or eTx)
————
572-Pin FlipChip FBGA24(RD or eTx) +24(Rx, Tx, or eTx)24(RD or eTx) + 24(Rx, Tx, or eTx)24(RD or eTx) + 24(Rx, Tx or eTx)24(RD or eTx) + 24(Rx, Tx or eTx)
——
780-Pin FlipChip FBGA28(RD or eTx) + 28(Rx, Tx, or eTx)28(RD or eTx) + 28(Rx, Tx or eTx)28(RD or eTx) + 28(Rx, Tx or eTx)28(RD or eTx) + 28((Rx, Tx or eTx)28(RD or eTx)+ 28(Rx, Tx or eTx)28(RD or eTx) + 28(Rx, Tx or eTx)
1152-Pin FlipChip FBGA
——
32(RD or eTx) + 32(Rx, Tx, or eTx)32(RD or eTx) + 32(Rx, Tx or eTx)48(RD or eTx) + 48(Rx, Tx or eTx)48(RD or eTx) + 48(Rx, Tx or eTx)
Table8–2.LVDS Channels Supported in Arria II GX Device Column I/O Banks (Note1), (2), (3), (4), (5), (6)(Part 1 of 2)
DeviceEP2AGX45EP2AGX65EP2AGX95EP2AGX125EP2AGX190
358-Pin FlipChip UBGA25(RD or eTx) + 24(Rx, Tx, or eTx) 25(RD or eTx) + 24(Rx, Tx, or eTx)
———
572-Pin FlipChip FBGA33(RD or eTx) + 32(Rx, Tx, or eTx) 33(RD or eTx) + 32(Rx, Tx, or eTx)33(RD or eTx) + 32(Rx, Tx, or eTx)33(RD or eTx) + 32(Rx, Tx, or eTx)
—
780-Pin FlipChip FBGA57(RD or eTx) + 56(Rx, Tx, or eTx)57(RD or eTx) + 56(Rx, Tx, or eTx)57(RD or eTx) + 56(Rx, Tx, or eTx)57(RD or eTx) + 56(Rx, Tx, or eTx)57(RD or eTx) + 56(Rx, Tx, or eTx)
1152-Pin FlipChip FBGA
——
73(RD or eTx) + 72(Rx, Tx, or eTx)73(RD or eTx) + 72(Rx, Tx, or eTx)97(RD or eTx) + 96(Rx, Tx, or eTx)
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 8:High-Speed Differential I/O Interfaces and DPA in ArriaII Devices
Locations of the I/O Banks
Table8–2.LVDS Channels Supported in Arria II GX Device Column I/O Banks (Note1), (2), (3), (4), (5), (6)(Part 2 of 2)
DeviceEP2AGX260
358-Pin FlipChip UBGA
—
572-Pin FlipChip FBGA
—
780-Pin FlipChip FBGA57(RD or eTx) + 56(Rx, Tx, or eTx)
1152-Pin FlipChip FBGA97(RD or eTx) + 96(Rx, Tx, or eTx)
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 8:High-Speed Differential I/O Interfaces and DPA in ArriaII DevicesDifferential Receiver
Figure8–9 shows the possible phase relationships between the DPA clocks and the incoming serial data.
Figure8–9.DPA Clock Phase to Serial Data Timing Relationship (Note1)
rx_in0?45?90?135?180?225?270?315?D0D1D2D3D4DnTvcoArria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 8:High-Speed Differential I/O Interfaces and DPA in ArriaII DevicesDifferential Receiver
Figure8–11 shows a preset value of 4-bit times before rollover occurs. The rx_cda_max signal pulses for one rx_outclock cycle to indicate that rollover has occurred.
Figure8–11.Receiver Data Re-Alignment Rollover
rx_inclockrx_channel_data_alignrx_outclockrx_cda_maxDeserializer
The deserializer, which includes shift registers and parallel load registers, converts the serial data from the bit slip to parallel data before sending the data to the FPGA fabric. The deserialization factor supported is 4, 6, 7, 8, or 10. You can bypass the deserializer to support DDR (x2) and SDR (x1) operations, as shown in Figure8–12. You cannot use the DPA and data realignment circuit when the deserializer is bypassed. The IOE contains two data input registers that can operate in DDR or SDR mode.
Figure8–12.Deserializer Bypass(Note1), (2), (3)
IOE Supports SDR, DDR, or Non-Registered Datapath
2
2
LVDS Receiver
+rx_out
IOE
rx_in
Synchronizer
DeserializerDeserializerDOUTDIN
Bit Slip
DOUTDIN
DOUTDIN
PA CircuitryDP
Retimed
Data
DIN
FPGAFabric
2
(LOAD_EN, diffioclk)
diffioclk
LVDS_diffiioclkDPA_diffioclkClock Multiplexerp
DPPA Clock
3
rx_divfwdclkrx_outclock
(DPA_LOAD_EN,
DPA_diffioclk,rx_divfwdclk)
3
(LVDS_LOAD_EN,LVDS_diffioclk,rx_outclk)
8 Serial LVDSLClock Phases
PLL (4)
Notes to Figure8–12:
(1)All disabled blocks and signals are grayed out.
(2)In DDR mode, rx_inclock clocks the IOE register. In SDR mode, data is directly passed through the IOE.(3)In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.(4)Arria II GX center/corner PLL or Arria II GZ left/right PLL.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 8:High-Speed Differential I/O Interfaces and DPA in ArriaII Devices
Differential Receiver
Arria II Device Handbook Volume 1: Device Interfaces and Integration
FPGA可编程逻辑器件芯片EP2AGX65DF29I3N中文规格书 - 图文
