output begins at the column address last specified in the READ PAGE (00h-30h) com-mand. The RANDOM DATA READ TWO-PLANE (06h-E0h) command is used to enabledata output in the other cache registers.
Figure 38: READ PAGE (00h-30h) Operation
Cycle typeCommandAddressAddressAddressAddressAddressCommandDOUTDOUTDOUTI/O[7:0]00hC1C2R1R2R330htWBtRtRRDnDn+1Dn+2RDYFigure 39: READ PAGE (00h-30h) Operation with Internal ECC Enabled
tR_ECCRDYI/O[7:0]00hAddressAddressAddressAddressAddress30h70hStatus00hDOUT (serial access)SR bit 0 = 0 READ successfulSR bit 1 = 0 READ error
READ PAGE CACHE SEQUENTIAL (31h)
The READ PAGE CACHE SEQUENTIAL (31h) command reads the next sequential pagewithin a block into the data register while the previous page is output from the cacheregister. This command is accepted by the die (LUN) when it is ready
(RDY = 1, ARDY = 1). It is also accepted by the die (LUN) during READ PAGE CACHE(31h, 00h-31h) operations (RDY = 1 and ARDY = 0).
To issue this command, write 31h to the command register. After this command is is-sued, R/B# goes LOW and the die (LUN) is busy (RDY = 0, ARDY = 0) for tRCBSY. AftertRCBSY, R/B# goes HIGH and the die (LUN) is busy with a cache operation
(RDY = 1, ARDY = 0), indicating that the cache register is available and that the specifiedpage is copying from the NAND Flash array to the data register. At this point, data canbe output from the cache register beginning at column address 0. The RANDOM DATAREAD (05h-E0h) command can be used to change the column address of the data beingoutput from the cache register.
The READ PAGE CACHE SEQUENTIAL (31h) command can be used to cross block
boundaries. If the READ PAGE CACHE SEQUENTIAL (31h) command is issued after thelast page of a block is read into the data register, the next page read will be the next logi-cal block in which the 31h command was issued. Do not issue the READ PAGE CACHESEQUENTIAL (31h) to cross die (LUN) boundaries. Instead, issue the READ PAGECACHE LAST (3Fh) command.
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Read Operations
Figure 40: READ PAGE CACHE SEQUENTIAL (31h) Operation
Cycle typeCommandAddress x5CommandCommandDOUTDOUTDOUTCommandDOUTI/O[7:0]00hPage Address M30htWBtRRR31htWBtRCBSYtRRD0…Dn31htWBtRCBSYtRRD0RDY
Page MPage M+1READ PAGE CACHE RANDOM (00h-31h)
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4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
Program Operations
Program Operations
Program operations are used to move data from the cache or data registers to the NANDarray. During a program operation the contents of the cache and/or data registers aremodified by the internal control logic.
Within a block, pages must be programmed sequentially from the least significant pageaddress to the most significant page address (0, 1, 2, ….., 63). During a program opera-tion, the contents of the cache and/or data registers are modified by the internal controllogic.
Program Operations
The PROGRAM PAGE (80h-10h) command, when not preceded by the PROGRAM PAGETWO-PLANE (80h-11h) command, programs one page from the cache register to theNAND Flash array. When the die (LUN) is ready (RDY = 1, ARDY = 1), the host shouldcheck the FAIL bit to verify that the operation has completed successfully.Program Cache Operations
The PROGRAM PAGE CACHE (80h-15h) command can be used to improve program op-eration system performance. When this command is issued, the die (LUN) goes busy(RDY = 0, ARDY = 0) while the cache register contents are copied to the data register,and the die (LUN) is busy with a program cache operation (RDY = 1, ARDY = 0. Whilethe contents of the data register are moved to the NAND Flash array, the cache registeris available for an additional PROGRAM PAGE CACHE (80h-15h) or PROGRAM PAGE(80h-10h) command.
For PROGRAM PAGE CACHE series (80h-15h) operations, during the die (LUN) busytimes, tCBSY and tLPROG, when RDY = 0 and ARDY = 0, the only valid commands arestatus operations (70h, 78h) and reset (FFh). When RDY = 1 and ARDY = 0, the only validcommands during PROGRAM PAGE CACHE series (80h-15h) operations are status op-erations (70h, 78h), PROGRAM PAGE CACHE (80h-15h), PROGRAM PAGE (80h-10h),RANDOM DATA INPUT (85h), PROGRAM FOR INTERNAL DATA INPUT (85h), and RE-SET (FFh).
Two-Plane Program Operations
The PROGRAM PAGE TWO-PLANE (80h-11h) command can be used to improve pro-gram operation system performance by enabling multiple pages to be moved from thecache registers to different planes of the NAND Flash array. This is done by prependingone or more PROGRAM PAGE TWO-PLANE (80h-11h) commands in front of the PRO-GRAM PAGE (80h-10h) command.Two-Plane Program Cache Operations
The PROGRAM PAGE TWO-PLANE (80h-11h) command can be used to improve pro-gram cache operation system performance by enabling multiple pages to be movedfrom the cache registers to the data registers and, while the pages are being transferredfrom the data registers to different planes of the NAND Flash array, free the cache regis-ters to receive data input from the host. This is done by prepending one or more PRO-GRAM PAGE TWO-PLANE (80h-11h) commands in front of the PROGRAM PAGECACHE (80h-15h) command.
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4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
Program Operations
PROGRAM PAGE (80h-10h)
The PROGRAM PAGE (80h-10h) command enables the host to input data to a cache reg-ister, and moves the data from the cache register to the specified block and page ad-dress in the array of the selected die (LUN). This command is accepted by the die (LUN)when it is ready (RDY = 1, ARDY = 1). It is also accepted by the die (LUN) when it is busywith a PROGRAM PAGE CACHE (80h-15h) operation (RDY = 1, ARDY = 0).
To input a page to the cache register and move it to the NAND array at the block andpage address specified, write 80h to the command register. Unless this command hasbeen preceded by a PROGRAM PAGE TWO-PLANE (80h-11h) command, issuing the 80hto the command register clears all of the cache registers' contents on the selected target.Then write n address cycles containing the column address and row address. Data inputcycles follow. Serial data is input beginning at the column address specified. At any timeduring the data input cycle the RANDOM DATA INPUT (85h) and PROGRAM FOR IN-TERNAL DATA INPUT (85h) commands may be issued. When data input is complete,write 10h to the command register. The selected LUN will go busy(RDY = 0, ARDY = 0) for tPROG as data is transferred.
To determine the progress of the data transfer, the host can monitor the target's R/B#signal or, alternatively, the status operations (70h, 78h) may be used. When the die(LUN) is ready (RDY = 1, ARDY = 1), the host should check the status of the FAIL bit.In devices that have more than one die (LUN) per target, during and following inter-leaved die (multi-LUN) operations, the READ STATUS ENHANCED (78h) commandmust be used to select only one die (LUN) for status output. Use of the READ STATUS(70h) command could cause more than one die (LUN) to respond, resulting in bus con-tention.
The PROGRAM PAGE (80h-10h) command is used as the final command of a two-planeprogram operation. It is preceded by one or more PROGRAM PAGE TWO-PLANE(80h-11h) commands. Data is transferred from the cache registers for all of the ad-dressed planes to the NAND array. The host should check the status of the operation byusing the status operations (70h, 78h).
When internal ECC is enabled, the duration of array programming time is tPROG_ECC.During tPROG_ECC, the internal ECC generates parity bits when error detection is com-plete.
Figure 44: PROGRAM PAGE (80h-10h) Operation
Cycle typeCommandAddressAddressAddressAddressAddresstADLDINDINDINDINCommandCommandDOUTI/O[7:0]80hC1C2R1R2R3D0D1…Dn10htWB tPROG_ECCtPROG or70hStatusRDYPROGRAM PAGE CACHE (80h-15h)
The PROGRAM PAGE CACHE (80h-15h) command enables the host to input data to acache register; copies the data from the cache register to the data register; then movesthe data register contents to the specified block and page address in the array of the se-lected die (LUN). After the data is copied to the data register, the cache register is availa-
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4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
Program Operations
PROGRAM PAGE TWO-PLANE (80h-11h)
The PROGRAM PAGE TWO-PLANE (80h-11h) command enables the host to input datato the addressed plane's cache register and queue the cache register to ultimately bemoved to the NAND Flash array. This command can be issued one or more times. Eachtime a new plane address is specified that plane is also queued for data transfer. To in-put data for the final plane and to begin the program operation for all previously
queued planes, issue either the PROGRAM PAGE (80h-10h) command or the PROGRAMPAGE CACHE (80h-15h) command. All of the queued planes will move the data to theNAND Flash array. This command is accepted by the die (LUN) when it is ready(RDY = 1).
To input a page to the cache register and queue it to be moved to the NAND Flash arrayat the block and page address specified, write 80h to the command register. Unless thiscommand has been preceded by a PROGRAM PAGE TWO-PLANE (80h-11h) command,issuing the 80h to the command register clears all of the cache registers' contents on theselected target. Write five address cycles containing the column address and row ad-dress; data input cycles follow. Serial data is input beginning at the column address
specified. At any time during the data input cycle, the RANDOM DATA INPUT (85h) andPROGRAM FOR INTERNAL DATA INPUT (85h) commands can be issued. When datainput is complete, write 11h to the command register. The selected die (LUN) will gobusy (RDY = 0, ARDY = 0) for tDBSY.
To determine the progress of tDBSY, the host can monitor the target's R/B# signal or,alternatively, the status operations (70h, 78h) can be used. When the LUN's statusshows that it is ready (RDY = 1), additional PROGRAM PAGE TWO-PLANE (80h-11h)commands can be issued to queue additional planes for data transfer. Alternatively, thePROGRAM PAGE (80h-10h) or PROGRAM PAGE CACHE (80h-15h) commands can be is-sued.
When the PROGRAM PAGE (80h-10h) command is used as the final command of a two-plane program operation, data is transferred from the cache registers to the NANDFlash array for all of the addressed planes during tPROG. When the die (LUN) is ready(RDY = 1, ARDY = 1), the host should check the status of the FAIL bit for each of theplanes to verify that programming completed successfully.
When the PROGRAM PAGE CACHE (80h-15h) command is used as the final commandof a program cache two-plane operation, data is transferred from the cache registers tothe data registers after the previous array operations finish. The data is then movedfrom the data registers to the NAND Flash array for all of the addressed planes. This oc-curs during tCBSY. After tCBSY, the host should check the status of the FAILC bit for
each of the planes from the previous program cache operation, if any, to verify that pro-gramming completed successfully.
For the PROGRAM PAGE TWO-PLANE (80h-11h), PROGRAM PAGE (80h-10h), and PRO-GRAM PAGE CACHE (80h-15h) commands, see Two-Plane Operations for two-plane ad-dressing requirements.
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MEMORY存储芯片PC28F256M29EWHA中文规格书 - 图文
