voltage, and temperature (PVT) variations. This phase-shift circuitry has been enhanced in StratixII and StratixIIGX devices to support more phase-shift options with less jitter.
Besides the DQS dedicated phase-shift circuitry, each DQS and DQSn pin has its own DQS logic block that sets the delay for the signal input to the pin. Using the DQS dedicated phase-shift circuitry with the DQS logic block allows for phase-shift fine-tuning. Additionally, every IOE in a StratixII or StratixIIGX device contains six registers and one latch to achieve DDR operation.
DDR Memory Interface Pins
StratixII and StratixIIGX devices use data (DQ), data strobe (DQS and DQSn), and clock pins to interface with external memory.
Figure3–6 shows the DQ, DQS, and DQSn pins in the StratixII or
StratixIIGX I/O banks on the top of the device. A similar arrangement is repeated at the bottom of the device.
Figure3–6.DQ and DQS Pins Per I/O Bank
Up to 8 Sets ofDQ & DQS PinsDQPinsUp to 10 Sets ofDQ & DQS PinsDQPinsPLL 11I/OBank 3I/OBank 11PLL 5I/OBank 9DQSPhaseShiftCircuitryI/OBank 4DQSnPinDQSPinDQSnPinDQSPinData and Data Strobe Pins
StratixII and StratixIIGX data pins for the DDR memory interfaces are called DQ pins. StratixII and StratixIIGX devices can use either
bidirectional data strobes or unidirectional read clocks. Depending on the external memory interface, either the memory device’s read data strobes or read clocks feed the StratixII or StratixIIGX DQS (and DQSn) pins.
Stratix II Device Handbook, Volume 2
External Memory Interfaces in StratixII and StratixIIGX Devices
StratixII and StratixIIGX DQS pins connect to the DQS pins in DDR and DDR2 SDRAM interfaces or to the QK pins in RLDRAM II interfaces. The DQSn pins are not used in these interfaces. Connect the StratixII or
StratixIIGX DQS and DQSn pins to the QDRII SRAM CQ and CQ# pins, respectively.
In every StratixII or StratixIIGX device, the I/O banks at the top (I/O banks 3 and 4) and bottom (I/O banks 7 and 8) of the device support DDR memory up to 300MHz/600 Mbps (with RLDRAM II). These I/O banks support DQS signals and its complement DQSn signals with DQ bus modes of ×4, ×8/×9, ×16/×18, or ×32/×36.
In ×4 mode, each DQS/DQSn pin drives up to four DQ pins within that group. In ×8/×9 mode, each DQS/DQSn pin drives up to nine DQ pins within that group to support one parity bit and the eight data bits. If the parity bit or any data bit is not used, the extra DQ pins can be used as regular user I/O pins. Similarly, with ×16/×18 and ×32/×36modes, each DQS/DQSn pin drives up to 18 and 36 DQ pins respectively. There are two parity bits in the ×16/×18 mode and four parity bits in the ×32/×36 mode. Tables3–3 through 3–6 show the number of DQS/DQ groups and non-DQS /DQ supported in each StratixII or StratixIIGX density/package combination, respectively, for DLL-based implementations.
Table3–3.Stratix II DQS and DQ Bus Mode Support(Part 1 of2)Device
EP2S15EP2S30EP2S60
Note(1)
Number of Number of ×16/×18 Groups×32/×36 Groups
04040480488488
00000040044044
Package
484-pin FineLine BGA672-pin FineLine BGA484-pin FineLine BGA672-pin FineLine BGA484-pin FineLine BGA672-pin FineLine BGA1,020-pin FineLine BGA
Number of ×4Groups
818818818368183636183636
Number of ×8/×9 Groups
4848481848181881818
EP2S90484-pin Hybrid FineLine BGA780-pin FineLine BGA1,020-pin FineLine BGA1,508-pin FineLine BGA
EP2S130780-pin FineLine BGA
1,020-pin FineLine BGA1,508-pin FineLine BGA
Stratix II Device Handbook, Volume 2
Device Configuration Pins
Stratix II Device Handbook, Volume 2
Configuring StratixII and StratixIIGX Devices
Table7–22.Dedicated Configuration Pins on the Stratix II and StratixIIGX Device(Part 10 of10)Pin NamenCS/CS
User Mode
I/O
Configuration Scheme
PPA
Pin Type
Input
Description
Chip-select inputs. A low on nCS and a high on CS select the target device for configuration. The nCS and CS pins must be held active during configuration and initialization.During the PPA configuration mode, it is only required to use either the nCS or CS pin.
Therefore, if only one chip-select input is used, the other must be tied to the active state. For example, nCS can be tied to ground while CS is toggled to control configuration.
In non-PPA schemes, it functions as a user I/O pin during configuration, which means it is tri-stated.
After PPA configuration, nCS and CS are available as user I/O pins and the state of these pins depends on the Dual-Purpose Pin settings.
RUnLU
N/A if using Remote System UpgradeI/O if notRemote System Upgrade in FPP, PS or PPA
Input
Input that selects between remote update and local update. A logic high (1.5-V, 1.8-V, 2.5-V, 3.3-V) selects remote update and a logic low selects local update.
When not using remote update or local update configuration modes, this pin is available as general-purpose user I/O pin.
PGM[2..0]
N/A if using Remote System UpgradeI/O if not using
Remote System Upgrade in FPP, PS or PPA
Output
These output pins select one of eight pages in the memory (either flash or enhanced
configuration device) when using a remote system upgrade mode.
When not using remote update or local update configuration modes, these pins are available as general-purpose user I/O pins.
Stratix II Device Handbook, Volume 2
Device Configuration Pins
Table7–23 describes the optional configuration pins. If these optional configuration pins are not enabled in the QuartusII software, they are available as general-purpose user I/O pins. Therefore, during
configuration, these pins function as user I/O pins and are tri-stated with weak pull-up resistors.
Table7–23.Optional Configuration PinsPin NameCLKUSR
User Mode
N/A if option is on. I/O if option is off.
Pin Type
Input
Description
Optional user-supplied clock input synchronizes the initialization of one or more devices. This pin is enabled by turning on the Enable user-supplied start-up clock (CLKUSR) option in the QuartusII software.
INIT_DONE
N/A if option is on. Output open-drainStatus pin can be used to indicate when the device I/O if option is off.has initialized and is in user mode. When nCONFIG is
low and during the beginning of configuration, the INIT_DONE pin is tri-stated and pulled high due to an external 10-k? pull-up resistor. Once the option bit to enable INIT_DONE is programmed into the device (during the first frame of configuration data), the INIT_DONE pin will go low. When initialization is complete, the INIT_DONE pin will be released and pulled high and the device enters user mode. Thus, the monitoring circuitry must be able to detect a low-to-high transition. This pin is enabled by turning on the Enable INIT_DONE output option in the QuartusII software.N/A if option is on. I/O if option is off.
Input
Optional pin that allows the user to override all
tri-states on the device. When this pin is driven low, all I/O pins are tri-stated; when this pin is driven high, all I/O pins behave as programmed. This pin is enabled by turning on the Enable device-wide output enable (DEV_OE) option in the QuartusII software.Optional pin that allows you to override all clears on all device registers. When this pin is driven low, all registers are cleared; when this pin is driven high, all registers behave as programmed. This pin is enabled by turning on the Enable device-wide reset (DEV_CLRn) option in the QuartusII software.
DEV_OE
DEV_CLRn
N/A if option is on. I/O if option is off.
Input
Stratix II Device Handbook, Volume 2
FPGA可编程逻辑器件芯片EP1S10F672C7N中文规格书 - 图文
