1Spartan-3 FPGA Family
Data Sheet
Product Specification
DS099 June 27, 2013
Module 1:
Introduction and Ordering Information
DS099 (v3.1) June 27, 2013??????
IntroductionFeatures
Architectural OverviewArray Sizes and ResourcesUser I/O ChartOrdering Information
Module 4: Pinout Descriptions
DS099 (v3.1) June 27, 2013???
Pin Descriptions?
Pin Behavior During ConfigurationPackage OverviewPinout Tables?
Footprints
Module 2: Functional Description
DS099 (v3.1) June 27, 2013?
Input/Output Blocks (IOBs)?????
IOB Overview
SelectIO? Interface I/O Standards
Configurable Logic Blocks (CLBs)Block RAMDedicated Multipliers
???
Digital Clock Manager (DCM)Clock NetworkConfiguration
Module 3:
DC and Switching Characteristics
DS099 (v3.1) June 27, 2013?
DC Electrical Characteristics?????
????
Absolute Maximum RatingsSupply Voltage SpecificationsRecommended Operating ConditionsDC CharacteristicsI/O Timing
Internal Logic TimingDCM Timing
Configuration and JTAG Timing
Switching Characteristics
DS099 June 27, 2013Product Specification
Spartan-3 FPGA Family:
Introduction and Ordering Information
DS099 (v3.1) June 27, 2013
Product Specification
Introduction
The Spartan?-3 family of Field-Programmable Gate Arrays is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. The
eight-member family offers densities ranging from 50,000 to 5,000,000 system gates, as shown in Table1.
The Spartan-3 family builds on the success of the earlier Spartan-IIE family by increasing the amount of logic
resources, the capacity of internal RAM, the total number of I/Os, and the overall level of performance as well as by improving clock management functions. Numerous enhancements derive from the Virtex?-II platform technology. These Spartan-3 FPGA enhancements,
combined with advanced process technology, deliver more functionality and bandwidth per dollar than was previously possible, setting new standards in the programmable logic industry.
Because of their exceptionally low cost, Spartan-3 FPGAs are ideally suited to a wide range of consumer electronics applications, including broadband access, home networking, display/projection and digital television equipment.
The Spartan-3 family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial cost, the lengthy development cycles, and the inherent inflexibility of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary, an impossibility with ASICs.
Table 1:Summary of Spartan-3 FPGA Attributes
DeviceXC3S50(2)XC3S200(2)XC3S400(2)XC3S1000(2)XC3S1500XC3S2000XC3S4000XC3S5000
CLB Array
(One CLB = Four Slices)System Equivalent
GatesLogic Cells(1)Total
RowsColumns
CLBs 50K200K400K1M1.5M2M4M5M
1,7284,3208,06417,28029,95246,08062,20874,880
16243248648096104
1220284052647280
1924808961,9203,3285,1206,9128,320
Features
??
Low-cost, high-performance logic solution for high-volume,consumer-oriented applications?Densities up to 74,880 logic cellsSelectIO? interface signaling?Up to 633 I/O pins?622+ Mb/s data transfer rate per I/O?18 single-ended signal standards?8 differential I/O standards including LVDS, RSDS?Termination by Digitally Controlled Impedance?Signal swing ranging from 1.14V to 3.465V?Double Data Rate (DDR) support?DDR, DDR2 SDRAM support up to 333Mb/sLogic resources?Abundant logic cells with shift register capability?Wide, fast multiplexers?Fast look-ahead carry logic?Dedicated 18 x 18 multipliers?JTAG logic compatible with IEEE 1149.1/1532SelectRAM? hierarchical memory?Up to 1,872 Kbits of total block RAM?Up to 520 Kbits of total distributed RAMDigital Clock Manager (up to four DCMs)?Clock skew elimination?Frequency synthesis?High resolution phase shifting
Eight global clock lines and abundant routing
Fully supported by Xilinx ISE? and WebPACK? softwaredevelopment systems
MicroBlaze? and PicoBlaze? processor, PCI?,PCIExpress? PIPE Endpoint, and other IP coresPb-free packaging options
Automotive Spartan-3 XA Family variant
?
??
?????
Distributed Block
Dedicated
RAM Bits RAM Bits DCMs
Multipliers
(K=1024)(K=1024)
12K30K56K120K208K320K432K520K
72K216K288K432K576K720K1,728K1,872K
4121624324096104
24444444
Maximum
Max.
Differential
User I/O
I/O Pairs124173264391487565633633
5676116175221270300300
Notes:
1.2.Logic Cell = 4-input Look-Up Table (LUT) plus a ‘D’ flip-flop. \otal CLBs\These devices are available in Xilinx Automotive versions as described in DS314: Spartan-3 Automotive XA FPGA Family.DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Introduction and Ordering Information
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Introduction and Ordering Information
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Introduction and Ordering Information
Table3 shows the number of user I/Os as well as the number of differential I/O pairs available for each device/package combination.
Table 3:Spartan-3 Device I/O Chart
Available User I/Os and Differential (Diff) I/O Pairs by Package Type
PackageFootprint(mm)Device
XC3S50XC3S200XC3S400XC3S1000XC3S1500XC3S2000XC3S4000XC3S5000
VQ100VQG10016x16
CP132(1)CPG1328x8
Diff
TQ144TQG14422x22
PQ208PQG20830.6x30.6
FT256FTG25617x17
FG320FGG32024x19
FG456FGG45623x23
FG676FGG67627x27
FG900FGG90031x31
FG1156(1)FGG115635x35User
––––––
UserDiffUser
6363––––––
2929––––––
UserDiffUserDiffUserDiffUserDiffUserDiffUserDiffUserDiff
979797–––––
464646–––––
124141141–––––
566262–––––
–173173173––––
–767676––––
––221221221–––
––100100100–––
––264333333333––
––116149149149––
–––391487489489489
–––175221221221221
–––––565633633
–––––270300300
Diff
––––––
89(1)44(1)–––––––
–––––––
712(1)312(1)784(1)344(1)
Notes:
1.2.3.
The CP132, CPG132, FG1156, and FGG1156 packages are discontinued. Seehttp://www.xilinx.com/support/documentation/spartan-3_customer_notices.htm.All device options listed in a given package column are pin-compatible.User = Single-ended user I/O pins. Diff = Differential I/O pairs.
Package Marking
Figure2 shows the top marking for Spartan-3 FPGAs in the quad-flat packages. Figure3 shows the top marking for
Spartan-3 FPGAs in BGA packages except the 132-ball chip-scale package (CP132 and CPG132). The markings for the BGA packages are nearly identical to those for the quad-flat packages, except that the marking is rotated with respect to the ball A1 indicator. Figure4 shows the top marking for Spartan-3 FPGAs in the CP132 and CPG132 packages.
The “5C” and “4I” part combinations may be dual marked as “5C/4I”. Devices with the dual mark can be used as either -5C or -4I devices. Devices with a single mark are only guaranteed for the marked speed grade and temperature range. Some specifications vary according to mask revision. Mask revision E devices are errata-free. All shipments since 2006 have been mask revision E.
X-Ref Target - Figure 2Mask Revision CodeFabrication CodeSPARTANDevice TypePackageSpeed GradeTemperature RangeRProcess TechnologyDate CodeLot CodeXC3S400TMPQ208EGQ0525D1234567A4CPin P1DS099-1_03_050305Figure 2:Spartan-3 FPGA QFP Package Marking Example for Part Number XC3S400-4PQ208C
DS099 (v3.1) June 27, 2013Product Specification
FPGA可编程逻辑器件芯片XC2S15-6CSG144I中文规格书 - 图文
