TDI1x0100DQDsdQINTESTLE1IOB.I01x0100sdDQDQLE1IOB.OIOB.T1x0100DQDsdQ001EXTESTLESHIFTCLOCK DATAREGISTERTDOUPDATEINTEST is OR'd with EXTESTUG191_c3_03_050406
Figure 3-3:Virtex-5 Family Boundary-Scan Logic
Bit Sequence Boundary-Scan Register
The order of each non-TAP IOB is described in this section. The input is first, then the output, and finally the 3-state IOB control. The 3-state IOB control is closest to the TDO. The input-only pins contribute only the input bit to the Boundary-Scan I/O data register. The bit sequence of the device is obtainable from the Boundary-Scan Description Language Files (BSDL files) for the Virtex-5 family. (These files can be obtained from the Xilinx software download area.) The bit sequence always has the same bit order and the same number of bits and is independent of the design.
Instruction Register
The Instruction Register (IR) for the Virtex-5 device is connected between TDI and TDO during an instruction scan sequence. In preparation for an instruction scan sequence, the instruction register is parallel-loaded with a fixed instruction capture pattern. This pattern is shifted out onto TDO (LSB first), while an instruction is shifted into the instruction register from TDI.
To determine the operation to be invoked, an OPCODE necessary for the Virtex-5
Boundary-Scan instruction set is loaded into the Instruction Register. The length of the IR is device size-specific. The IR is 10 bits wide for the Virtex-5 LX, LXT, SXT, FXT, and TXT platform devices. The FX100T, FX130T, and FX200T have 14 bits of OPCODE because they contain 2 PowerPC processors. The 4 or 8 most significant bits support the PowerPC440 embedded processor. The least significant 6 bits of the instruction code perform the same function for all Virtex-5 family members to support the new IEEE Standard 1532 for ISC devices. For PPC JTAG instruction, the least bits must be set to 100000 (20h). For PPC440 JTAG guidelines, refer to UG200, Embedded Processor Block in Virtex-5 FPGAs Reference Guide. Table3-3 lists the available instructions for Virtex-5 devices.
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Chapter 3:Boundary-Scan and JTAG Configuration
TDI?Notes:
IR[9:6]Reserved
IR[5]DONE
IR[4]INIT(1)
IR[3]ISC_ENABLED
IR[2]ISC_DONE
IR[1:0]0 1
?TDO
1.INIT is the status bit of the INIT_COMPLETE signal.
Figure 3-4:
Virtex-5 Device Instruction Capture Values Loaded into IR as Part of an Instruction Scan
Sequence
BYPASS Register
The other standard data register is the single flip-flop BYPASS register. It passes data serially from the TDI pin to the TDO pin during a bypass instruction. This register is initialized to zero when the TAP controller is in the CAPTURE-DR state.
Identification (IDCODE) Register
Virtex devices have a 32-bit identification register called the IDCODE register. The
IDCODE is based on the IEEE 1149.1 standard, and is a fixed, vendor-assigned value that is used to identify electrically the manufacturer and the type of device that is being
addressed. This register allows easy identification of the part being tested or programmed by Boundary-Scan, and it can be shifted out for examination by using the IDCODE instruction.
The last bit of the IDCODE is always 1 (based on JTAG IEEE 1149.1). The last three hex digits appear as 0x093. IDCODEs assigned to Virtex-5 FPGAs are shown in Table1-13, page29.
JTAG Configuration Register
The JTAG Configuration register is a 32-bit register. This register allows access to the configuration bus and readback operations.
USERCODE Register
The USERCODE instruction is supported in the Virtex-5 family. This register allows a user to specify a design-specific identification code. The USERCODE can be programmed into the device and can be read back for verification later. The USERCODE is embedded into the bitstream during bitstream generation (BitGen -g UserID option) and is valid only after configuration. If the device is blank or the USERCODE was not programmed, the USERCODE register contains 0xFFFFFFFF.
USER1, USER2, USER3, and USER4 Registers
The USER1, USER2, USER3, and USER4 registers are only available after configuration. These four registers must be defined by the user within the design. These registers can be accessed after they are defined by the TAP pins.
The BSCAN_VIRTEX5 library macro is required when creating these registers. This symbol is only required for driving internal scan chains (USER1, USER2, USER3, and USER4). A common input pin (TDI) and shared output pins represent the state of the TAP controller (RESET, SHIFT, and UPDATE). Virtex-5 TAP pins are dedicated and do not require the BSCAN_VIRTEX5 macro for normal Boundary-Scan instructions or operations. For HDL, the BSCAN_VIRTEX5 macro must be instantiated in the design.
Virtex-5 FPGA Configuration Guide
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Boundary-Scan for Virtex-5 Devices Using IEEE Standard 1149.1
Using Boundary-Scan in Virtex-5 Devices
Characterization data for some of the most commonly requested timing parameters shown in Figure3-5 are listed in DS202, Virtex-5 Data Sheet: DC and Switching Characteristics, in the Configuration Switching Characteristics table.
TMSTDI
TTAPTCKTTCKTAPTCK
TTCKTDOTDO
Data to be capturedData to be driven out
Data ValidData Valid
UG191_c3_05_050406
Figure 3-5:Virtex-5 Device Boundary-Scan Port Timing Waveforms
For further information on the startup sequence, bitstream, and internal configuration registers referenced here, refer to “Configuration Sequence” in Chapter1.
Configuring through Boundary-Scan
One of the most common Boundary-Scan vendor-specific instructions is the configure instruction. If the Virtex-5 device is configured via JTAG on power-up, it is advisable to tie the mode pins to the Boundary-Scan configuration mode settings: 101 (M2 = 1, M1 = 0, M0= 1).
The configuration flow for Virtex-5 device configuration with JTAG is shown in Figure3-6. The sections that follow describe how the Virtex-5 device can be configured as a single device through the Boundary-Scan or as part of a multiple-device scan chain.
A configured device can be reconfigured by toggling the TAP and entering a CFG_IN instruction after pulsing the PROGRAM pin or issuing the shut-down sequence. (Refer to Figure3-6.)
Designers who wish to implement the Virtex-5 JTAG configuration algorithm are encouraged to use the SVF-based flow provided in Xilinx application note XAPP058.
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Chapter 3:Boundary-Scan and JTAG Configuration
Multiple Device Configuration
It is possible to configure multiple Virtex-5 devices in a chain. (See Figure3-7.) The devices in the JTAG chain are configured one at a time. The multiple device configuration steps can be applied to any size chain.
Refer to the state diagram in Figure3-2 for the following TAP controller steps:1.2.3.4.5.6.7.
On power-up, place a logic 1 on the TMS and clock the TCK five times. This ensuresstarting in the TLR (Test-Logic-Reset) state.
Load the CFG_IN instruction into the target device (and BYPASS in all other devices).Go through the RTI state (RUN-TEST/IDLE).
Load in the configuration bitstream per step7 through step11 in Table3-4.Repeat step2 and step3 for each device.Reset all TAPs by clocking five 1s on TMS.Load the JSTART command into all devices.Go to the RTI state and clock TCK 12 times.
All devices are active at this point.
JTAG HeaderTDOVirtex-5FPGATDITMSTCKTDITMSTCKTDOVirtex-5FPGATDITMSTCKTDOVirtex-5FPGATDITMSTCKTDODevice 0Device 1Device 2UG191_c3_01_020609
Figure 3-7:Boundary-Scan Chain of Devices
If JTAG is the only configuration mode, then PROGRAM_B, INIT_B, and DONE can each be tied High to separate resistors as shown in the Master serial or Master/Slave Serial Mode Daisy Chain Configuration (see Figure2-3 and Figure2-4).
Virtex-5 FPGA Configuration Guide
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Boundary-Scan for Virtex-5 Devices Using IEEE Standard 1149.1
Reconfiguring through Boundary-Scan
The ability of Virtex-5 devices to perform partial reconfiguration is the reason that the configuration memory is not cleared when reconfiguring the device. When reconfiguring a chain of devices, refer to step3 in Table3-4. There are two methods to reconfigure Virtex-5 devices without possible internal contention. The first method is to pulse the
PROGRAM_B pin, resetting the internal configuration memory. The alternate method is to perform a shutdown sequence, placing the device in a safe state. The following shutdown sequence includes using internal registers. (For details on internal registers, refer to Chapter7, “Readback and Configuration Verification.”)
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2020
FPGA可编程逻辑器件芯片XQR17V16CC44M中文规格书 - 图文
