Pin NameVFS_0
DirectionInput
Description
e power supply pin for programming. When not used, connect to GND.
Dedicated System Monitor PinsAVDD_0(3)AVSS_0(3)VP_0(3)VN_0(3)VREFP_0(3)VREFN_ 0(3)
N/AN/AInputInputN/AN/A
System Monitor’s ADC analog positive supply voltage. Default connection is to VCCAUX.
System Monitor’s ADC analog ground reference. Default connection is to system GND via a ferrite bead.
System Monitor dedicated differential analog input (positive side).System Monitor dedicated differential analog input (negative side).1.25V reference input. Default connection is AVSS to enable the on-chip reference.
1.25V reference GND reference. Default connection is AVSS to enable the on-chip reference.
RocketIO Serial Transceiver Pins (GTXE1 and GTHE1_QUAD)MGTRXP[0:3]MGTRXN[0:3]MGTTXP[0:3]MGTTXN[0:3]MGTAVCCMGTAVCC_NMGTAVCC_SMGTAVTTMGTAVTT_NMGTAVTT_SMGTAVCC_LNMGTAVCC_LSMGTAVCC_RNMGTAVCC_RSMGTAVTT_LNMGTAVTT_LSMGTAVTT_RNMGTAVTT_RS
InputInputOutputOutputN/A
Positive differential receive port.Negative differential receive port.Positive differential transmit port.Negative differential transmit port.
Power-supply pin for GTXE1 transceiver’s mixed-signal circuitry and PLLs(4).Only available in Virtex-6 LXT and SXT devices.
Power-supply pin for GTXE1 transceiver’s TX and RX circuitry.(4).
N/A
Only available in Virtex-6 LXT and SXT devices.
Power-supply pin for transceiver mixed-signal circuitry left/north. Virtex-6 HXT devices only.
Power-supply pin for transceiver mixed-signal circuitry left/south. Virtex-6 HXT devices only.
Power-supply pin for transceiver mixed-signal circuitry right/north. Virtex-6 HXT devices only.
Power-supply pin for transceiver mixed-signal circuitry right/south. Virtex-6 HXT devices only.
Power-supply pin for TX and RX circuitry left/north. Virtex-6 HXT devices only.
Power-supply pin for TX and RX circuitry left/south. Virtex-6 HXT devices only.
Power-supply pin for TX and RX circuitry right/north. Virtex-6 HXT devices only.
Power-supply pin for TX and RX circuitry right/south. Virtex-6 HXT devices only.
N/AN/AN/AN/AN/AN/AN/AN/A
Virtex-6 FPGA PackagingUG365 (v2.6) October 3, 2024
Chapter 1:Packaging Overview
Figure1-7 shows the I/O and transceiver banks for the XC6VLX760. The black dots denote the global clock banks.
X-Ref Target - Figure 1-7IOOLBanks18(1)18(1)1717161615HROWBank40 I/OsIOCLBanks282827272626252524242323222221212024CenterBankCLBCLBCLBCLBCLBCLB0CFG0CFG0CFG0CFGCLBCLBCLBCLBCLBCLBCLBCLBMMCM17IOCRBanks383837373636353534343333323231313030IOORBanks 48(1)48(1)47474646454544444343424241(1)41(1)40(1)40(1)ug365_c1_07_111111CMTMMCM16MMCM15CMTMMCM14MMCM13CMTMMCM12MMCM111514141313121211(1)11(1)10(1)10(1)CMTMMCM10MMCM09CMTMMCM08MMCM07CMTMMCM06MMCM05CMTMMCM04MMCM03CMTMMCM02MMCM01CMTMMCM00Note:1. Unbonded banks in FF1760.Figure 1-7:XC6VLX760 Banks
Virtex-6 FPGA PackagingUG365 (v2.6) October 3, 2024
FF784/RF784 Package—LX75T, LX130T, LX195T, and LX240T
FF784/RF784 Package—LX75T, LX130T, LX195T, and LX240T
Table 2-2:FF784/RF784 Package—LX75T, LX130T, LX195T, and LX240T
Bank00000000000
Pin Description
Pin Number
M6L6D6C6N7M7F6N13N14P14R14
NoConnect (NC)
INIT_B_0DONE_0M1_0M2_0HSWAPEN_0PROGRAM_B_0M0_0AVSS_0AVDD_0VP_0VREFP_0
Virtex-6 FPGA PackagingUG365 (v2.6) October 3, 2024
FF784/RF784 Package—LX75T, LX130T, LX195T, and LX240T
Table 2-2:FF784/RF784 Package—LX75T, LX130T, LX195T, and LX240T (Cont’d)
Bank161616161616161616161616161616162323232323232323232323232323232323
Pin Description
Pin Number
H24G24D28E28E23D23F26F25F27E27G27G26D26C26G28H28W21V21AD22AC21V20V19AG22AF21AF22AE22AA21AB21Y18W18AG21AF20AD20
LX75TLX75TLX75TLX75TLX75TLX75TLX75TLX75TLX75TLX75TLX75TLX75TLX75TLX75TLX75TLX75TLX75TNoConnect (NC)
IO_L12P_VRN_16IO_L12N_VRP_16IO_L13P_16IO_L13N_16IO_L14P_16IO_L14N_VREF_16IO_L15P_16IO_L15N_16IO_L16P_16IO_L16N_16IO_L17P_16IO_L17N_16IO_L18P_16IO_L18N_16IO_L19P_16IO_L19N_16IO_L0P_23IO_L0N_23IO_L1P_23IO_L1N_23IO_L2P_23IO_L2N_23IO_L3P_23IO_L3N_23IO_L4P_23IO_L4N_VREF_23IO_L5P_23IO_L5N_23IO_L6P_23IO_L6N_23IO_L7P_23IO_L7N_23IO_L8P_SRCC_23
Virtex-6 FPGA PackagingUG365 (v2.6) October 3, 2024
Chapter 2:Pinout Tables
Table 2-7:FF1760 Package—LX550T and LX760 (Cont’d)
Bank212121212121212121212121212121212121222222222222222222222222222222
Pin Description
Pin Number
AT27AR27AK25AJ25AP26AP27AN24AN25AL24AM24AK23AK22AN26AM26AM23AN23AK24AL25AJ28AK28BA34BA35AY35AW35BB33BB34AT32AU33AV34AU34AV33AU32AP31
No Connect (NC)
IO_L11P_SRCC_21IO_L11N_SRCC_21IO_L12P_VRN_21IO_L12N_VRP_21IO_L13P_21IO_L13N_21IO_L14P_21IO_L14N_VREF_21IO_L15P_21IO_L15N_21IO_L16P_21IO_L16N_21IO_L17P_21IO_L17N_21IO_L18P_21IO_L18N_21IO_L19P_21IO_L19N_21IO_L0P_22IO_L0N_22IO_L1P_22IO_L1N_22IO_L2P_22IO_L2N_22IO_L3P_22IO_L3N_22IO_L4P_22IO_L4N_VREF_22IO_L5P_22IO_L5N_22IO_L6P_22IO_L6N_22IO_L7P_22
Virtex-6 FPGA PackagingUG365 (v2.6) October 3, 2024
FPGA可编程逻辑器件芯片XCZU11EG-1FFVC1760I中文规格书 - 图文
