Programmable IOE Delay
Table1–41 shows StratixIII IOE programmable delay settings. For more information on the annotation of delays in the IOE, refer to Figure7–7 in the StratixIII Device I/O Features chapter in volume 1 of the StratixIII Device Handbook.
Table1–41.StratixIII IOE Programmable Delay (Note1)
Fast Model
Min
Available
Offset
Settings
(2)
CommercialIndustrialC2
C3
C4
C4L
I3
I4
I4L
Parameter
VCCL = VCCL = 1.1V1.1VVCCL = VCCL = VCCL = VCCL = VCCL = VCCL = VCCL =
1.1V1.1V0.9V1.1V1.1V1.1V0.9VUnit
Max Offset
D1D2D3D4D5D6
157715156
000000
4422481625491452179
MaxOffset4912851806517503199
Max Max Max Max Max Max Max Max Max OffsetOffsetOffsetOffsetOffsetOffsetOffsetOffsetOffset7483872747726764305
8294123058872801337
9164423371884930370
8714273218844887354
8334113084808850339
8704333210845889354
9574643540928977389
9154483382887932371
8334113084808850339
pspspspspsps
Notes to Table1–41:
(1)You can set the parameter values in the QuartusII software by selecting D1, D2, D3, D4, D5, and D6 in the Assignment Name column.(2)The minimum offset represented in the table does not include the intrinsic delay.
Programmable Output Buffer Delay
Table1–42 lists the delay chain settings that control the rising and falling edge delays of the output buffer. Default delay is 0 ps.Table1–42.Programmable Output Buffer Delay(Note1)
Symbol
Parameter
Typical0 (default)
DOUTBUF
Rising and/or Falling Edge delay
50100150
Note to Table1–42:
(1)You can set the programmable output buffer delay in the QuartusII software by selecting the 'Output Buffer Delay
Control' assignment to either positive, negative or both edges with the specific values as stated in the table above in ps for the 'Output Buffer Delay' assignment.
Unitpspspsps
User I/O Pin Timing
Table1–43 through Table1–142 show user I/O pin timing for StratixIII devices. I/O buffer tsu, th, and tco are reported for the cases when I/O clock is driven by a non-PLL global clock (GCLK) and a PLL driven global clock (GCLK-PLL). For tsu, th and tco using regional clock, add the value from the adder tables listed for each device to the GCLK/GCLK-PLL values for the device.
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics
I/O Timing
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching CharacteristicsI/O Timing
Table1–105.EP3SE50 Column Pins output Timing Parameters (Part 6 of 6)
ParameterI/O Standard
Current StrengthFast ModelIndustrial
Commercial
C2VCCL=1.1V
C3VCCL=1.1V
C4VCCL=1.1V
VCCL=1.1V
C4L
VCCL=0.9V
I3VCCL=1.1V
I4VCCL=1.1V
VCCL=1.1V
I4LVCCL=0.9V
Unitsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns
ClockGCLK
4mA
GCLK PLLGCLK
6mA
1.2-V HSTL CLASS I
GCLK PLLGCLK
8mA
GCLK PLLGCLK
10mA
GCLK PLLGCLK
12mA
1.2-V HSTL CLASSII3.0-V PCI
GCLK PLLGCLK
16mA
GCLK PLLGCLK
—
GCLK PLLGCLK
—
GCLK PLL
tcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotco
2.9901.5072.9861.5033.0631.5803.0631.5803.0921.6093.0141.5302.9831.5002.9691.486
3.2031.6813.1991.6773.2741.7523.2741.7523.3141.7913.2251.7023.1921.6703.1771.656
4.5092.1814.5032.1744.5222.1924.5222.1924.5882.2584.4852.1544.4182.0874.3972.066
4.9015.4845.3515.5875.0205.5205.3875.5712.2952.5252.5242.4682.4022.6332.6362.4574.8945.4755.3425.5785.0135.5135.3805.5642.2882.5182.5172.4612.3952.6252.6282.4494.9035.4515.3185.5545.0225.5125.3795.5632.2962.5152.5142.4582.4032.6232.6262.4474.9035.4515.3185.5545.0225.5125.3795.5632.2962.5152.5142.4582.4032.6232.6262.4474.9785.4715.3385.5745.1005.5945.4615.6452.3712.5952.5942.5382.4812.7042.7072.5284.8675.3545.2215.4574.9855.4745.3415.5252.2592.4782.4772.4212.3652.5842.5872.4084.7965.2845.1515.3874.9155.4065.2735.4572.1892.4082.4072.3512.2952.5172.5202.3414.7725.2565.1235.3594.8875.3725.2395.4232.1662.3802.3792.3232.2692.4832.4862.307
3.0-VPCI-X
Table1–106 specifies EP3SE50 Row Pins Output Timing parameters for single-ended I/O standards.
Table1–106.EP3SE50 Row Pins output Timing Parameters (Part 1 of 5)
ParameterI/O Standard
Current StrengthFast ModelIndustrial
Commercial
C2VCCL=1.1V
C3VCCL=1.1V
C4VCCL=1.1V
VCCL=1.1V
C4L
VCCL=0.9V
I3VCCL=1.1V
I4VCCL=1.1V
VCCL=1.1V
I4LVCCL=0.9V
Unitsnsnsnsnsnsns
ClockGCLK
4mA
GCLK PLLGCLK
8mA
GCLK PLLGCLK
12mA
GCLK PLL
tcotcotcotcotcotco
3.1611.4883.0951.3953.0161.314
3.3951.6923.3241.5873.2351.493
4.7225.1175.6225.4865.7555.2475.7545.6185.8322.1012.1852.3812.4002.3492.3042.5052.5232.3444.6125.0055.5085.3725.6115.1345.6385.5025.6831.9712.0472.2372.2562.2052.1632.3562.3742.1954.5064.9055.4125.2765.4835.0355.5395.4035.5511.8521.9242.1092.1282.0772.0362.2242.2422.063
3.3-V LVTTL
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table1–106.EP3SE50 Row Pins output Timing Parameters (Part 2 of 5)
ParameterI/O Standard
Current StrengthFast ModelIndustrial
Commercial
C2VCCL=1.1V
C3VCCL=1.1V
C4VCCL=1.1V
VCCL=1.1V
C4L
VCCL=0.9V
I3VCCL=1.1V
I4VCCL=1.1V
VCCL=1.1V
I4LVCCL=0.9V
Unitsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns
ClockGCLK
4mA
tcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotco
3.1631.4983.0201.3183.1221.4423.0211.3192.9841.2823.0431.3562.9711.2693.1481.4683.0631.3613.0061.3123.4051.6503.1801.4773.1151.4023.0551.384
3.4021.6963.2391.4973.3561.6383.2441.5113.2061.4643.2681.5573.1901.4483.3931.6743.2901.5753.2461.5043.6631.8633.4611.6773.3591.5953.2851.575
4.7265.1225.6315.4955.7605.2555.7665.6305.8372.1092.1902.3862.4052.3542.3102.5102.5282.3494.5174.9205.4225.2865.4895.0475.5485.4125.5581.8581.9302.1152.1342.0832.0422.2312.2492.0704.6895.0855.5885.4525.7125.2155.7205.5845.7902.0532.1382.3382.3572.3062.2612.4632.4812.3024.5524.9435.4435.3075.5485.0735.5755.4385.6251.9001.9792.1742.1932.1422.0992.2992.3162.1374.4924.8785.3735.2375.4605.0055.5015.3655.5321.8181.8962.0862.1052.0542.0132.2062.2232.0444.5874.9785.4795.3435.6015.1075.6115.4745.6781.9472.0312.2272.2462.1952.1532.3522.3692.1904.4644.8495.3455.2095.4214.9755.4735.3365.4921.7831.8572.0472.0662.0151.9732.1662.1832.0044.7975.2115.7335.5975.8845.3475.8725.7365.9682.1852.2922.5102.5292.4782.4212.6422.6592.4804.6735.0765.5915.4555.7145.2105.7285.5915.7942.0302.1292.3402.3592.3082.2542.4682.4852.3064.5894.9905.5005.3645.5885.1215.6335.4975.6641.9192.0102.2142.2332.1822.1312.3382.3552.1765.2535.7176.2926.1566.3685.8676.4446.3086.4612.4592.5972.8492.8682.7872.7292.9843.0022.7934.9265.3495.8875.7515.9635.5026.0385.9016.0542.1682.2712.4892.5082.4272.4032.6232.6402.4314.7735.1995.7285.5925.8045.3345.8655.7295.8822.0692.1662.3882.4072.3262.2892.5172.5352.3264.6965.1065.6325.4965.7085.2395.7715.6355.7882.0122.1132.3232.3422.2612.2332.4452.4632.254
3.3-V LVCMOS
8mA
GCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLK
4mA
3.0-V LVTTL
8mA
12mA
4mA
3.0-V LVCMOS
8mA
4mA
2.5 V8mA
12mA
GCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLL
2mA
4mA
1.8 V
6mA
8mA
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table1–107.EP3SE50 Column Pins Input Timing Parameters (Part 2 of 3)
ParameterFast ModelIndustrial
Commercial
C2VCCL=1.1V
C3VCCL=1.1V
C4VCCL=1.1V
VCCL=1.1V
C4L
VCCL=0.9V
I3VCCL=1.1V
I4VCCL=1.1V
VCCL=1.1V
I4L
VCCL=0.9V
Units
I/O Standard
Clock
DIFFERENTIAL 1.2-V HSTL CLASSII
GCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLL
tsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuth
-0.7500.8681.100-0.847-0.7500.8681.100-0.847-0.7380.8561.112-0.859-0.7380.8561.112-0.859-0.7500.8681.100-0.847-0.7500.8681.100-0.847-0.7570.8751.093-0.840-0.7570.8751.093-0.840-0.7300.8481.120-0.867
-0.7740.9071.115-0.847-0.7740.9071.115-0.847-0.7630.8961.126-0.858-0.7630.8961.126-0.858-0.7740.9071.115-0.847-0.7740.9071.115-0.847-0.7800.9131.109-0.841-0.7800.9131.109-0.841-0.7510.8841.138-0.870
-1.133-1.250-1.376-1.319-1.616-1.252-1.377-1.323-1.6501.3191.777
1.4582.005
1.6062.218
1.5362.106
1.8332.110
1.4682.014
1.6162.229
1.5492.112
1.8682.160
nsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns
-1.377-1.556-1.717-1.634-1.631-1.558-1.721-1.632-1.677-1.133-1.250-1.376-1.319-1.616-1.252-1.377-1.323-1.6501.3191.777
1.4582.005
1.6062.218
1.5362.106
1.8332.110
1.4682.014
1.6162.229
1.5492.112
1.8682.160
DIFFERENTIAL 1.5-V HSTL CLASS I
-1.377-1.556-1.717-1.634-1.631-1.558-1.721-1.632-1.677-1.124-1.239-1.357-1.300-1.597-1.241-1.359-1.305-1.6321.3091.786
1.4472.016
1.5872.237
1.5172.125
1.8142.129
1.4572.025
1.5982.247
1.5312.130
1.8502.178
DIFFERENTIAL 1.5-V HSTL CLASSII
-1.387-1.567-1.736-1.653-1.650-1.569-1.739-1.650-1.695-1.124-1.239-1.357-1.300-1.597-1.241-1.359-1.305-1.6321.3091.786
1.4472.016
1.5872.237
1.5172.125
1.8142.129
1.4572.025
1.5982.247
1.5312.130
1.8502.178
DIFFERENTIAL 1.8-V HSTL CLASS I
-1.387-1.567-1.736-1.653-1.650-1.569-1.739-1.650-1.695-1.133-1.250-1.376-1.319-1.616-1.252-1.377-1.323-1.6501.3191.777
1.4582.005
1.6062.218
1.5362.106
1.8332.110
1.4682.014
1.6162.229
1.5492.112
1.8682.160
DIFFERENTIAL 1.8-V HSTL CLASSII
-1.377-1.556-1.717-1.634-1.631-1.558-1.721-1.632-1.677-1.133-1.250-1.376-1.319-1.616-1.252-1.377-1.323-1.6501.3191.777
1.4582.005
1.6062.218
1.5362.106
1.8332.110
1.4682.014
1.6162.229
1.5492.112
1.8682.160
DIFFERENTIAL 1.5-V SSTL CLASS I
-1.377-1.556-1.717-1.634-1.631-1.558-1.721-1.632-1.677-1.145-1.255-1.376-1.321-1.615-1.256-1.372-1.321-1.6461.3321.765
1.4662.000
1.6092.218
1.5392.104
1.8372.111
1.4752.010
1.6162.234
1.5482.114
1.8692.164
DIFFERENTIAL 1.5-V SSTL CLASSII
-1.364-1.548-1.714-1.631-1.627-1.551-1.721-1.633-1.676-1.145-1.255-1.376-1.321-1.615-1.256-1.372-1.321-1.6461.3321.765
1.4662.000
1.6092.218
1.5392.104
1.8372.111
1.4752.010
1.6162.234
1.5482.114
1.8692.164
DIFFERENTIAL 1.8-V SSTL CLASS I
-1.364-1.548-1.714-1.631-1.627-1.551-1.721-1.633-1.676-1.114-1.228-1.341-1.284-1.581-1.230-1.344-1.290-1.6171.2991.796
1.4362.027
1.5712.253
1.5012.141
1.7982.145
1.4462.036
1.5832.262
1.5162.145
1.8352.193
DIFFERENTIAL 1.8-V SSTL CLASSII
-1.397-1.578-1.752-1.669-1.666-1.580-1.754-1.665-1.710
Stratix III Device Handbook, Volume 2
FPGA可编程逻辑器件芯片EP1S25F780I8N中文规格书 - 图文
