SIIGX51003-2.2
Transceivers
Stratix?II GX devices incorporate dedicated embedded circuitry on the right side of the device, which contains up to 20 high-speed 6.375-Gbps serial transceiver channels. Each StratixIIGX transceiver block contains four full-duplex channels and supporting logic to transmit and receive high-speed serial data streams. The transceivers deliver bidirectional point-to-point data transmissions, with up to 51Gbps (6.375 Gbps per channel) of full-duplex data transmission per transceiver block.
Figure2–1 shows the function blocks that make up a transceiver channel within the StratixIIGX device.
Figure2–1.Stratix II GX Transceiver Block Diagram
PMA Analog SectionnDeserializer(1)ClockRecoveryUnitPCS Digital SectionFPGA FabricWordAlignerRateMatcherXAUILaneDeskew8B/10BDecoderByteDeserializerPhaseCompensationFIFO Bufferm(2)ByteOrderingReference ClockReceiver PLLTransmitter PLLnSerializer(1)8B/10B EncoderByteSerializerPhaseCompensationFIFO Bufferm(2)Reference ClockNotes to Figure2–1:(1)(2)
n represents the number of bits in each word that need to be serialized by the transmitter portion of the PMA or havebeen deserialized by the receiver portion of the PMA. n = 8, 10, 16, or 20.
m represents the number of bits in the word that pass between the FPGA logic and the PCS portion of the transceiver.m = 8, 10, 16, 20, 32, or 40.
Transceivers within each block are independent and have their own set of dividers. Therefore, each transceiver can operate at different frequencies. Each block can select from two reference clocks to provide two clock domains that each transceiver can select from.
I/O Structure
On-Chip Termination
Stratix II GX devices provide differential (for the LVDS technology I/O standard) and series on-chip termination to reduce reflections and
maintain signal integrity. On-chip termination simplifies board design by minimizing the number of external termination resistors required. Termination can be placed inside the package, eliminating small stubs that can still lead to reflections.
Stratix II GX devices provide four types of termination:
■■■■
Differential termination (RD)
Series termination (RS) without calibrationSeries termination (RS) with calibrationParallel termination (RT) with calibration
Table2–34 shows the Stratix II GX on-chip termination support per I/O bank.
Table2–34.On-Chip Termination Support by I/O Banks(Part 1 of2)On-Chip Termination Support
I/O Standard Support
3.3-V LVTTL3.3-V LVCMOS2.5-V LVTTL2.5-V LVCMOS1.8-V LVTTL1.8-V LVCMOS1.5-V LVTTL
Series termination without calibration
1.5-V LVCMOS SSTL-2 class I and IISSTL-18 class ISSTL-18 class II1.8-V HSTL class I1.8-V HSTL class II1.5-V HSTL class I1.2-V HSTL
Top and Bottom Banks
(3, 4, 7, 8)
vvvvvvvvvvvvvvv
Left Bank (1, 2)
vvvvvvvvv
v—
v
—
v
—
Stratix II GX Device Handbook, Volume 1
Stratix II GX Architecture
Stratix II GX Device Handbook, Volume 1
Stratix II GX Architecture
Table2–36 contains board design recommendations to ensure that nCEO can successfully drive nCE for all power supply combinations.
Table2–36.Board Design Recommendations for nCEO and nCE Input Buffer Power
Stratix IIGX nCEO VCCIO Voltage Level in I/O Bank 7nCE Input Buffer Power in
I/O Bank 3VCCIO = 3.3 VVCCIO = 2.5 VVCCIO = 1.8 VVCCIO = 1.5 VVCCIO = 1.2 V
VCCSEL high
(VCCIO Bank 3 = 1.5 V)
v(1), (2)v (1), (2)
v
v (3), (4)v (3), (4)v (4)
v (5)vv (6)
vv
Level shifter
required
v
Level shifter requiredLevel shifter required
VCCSEL high
(VCCIO Bank 3 = 1.8 V)
VCCSEL low (nCE powered
by VCCPD = 3.3 V)Notes to Table2–36:(1)(2)(3)(4)(5)(6)
Input buffer is 3.3-V tolerant.
The nCEO output buffer meets VOH (MIN) = 2.4 V.Input buffer is 2.5-V tolerant.
The nCEO output buffer meets VOH (MIN) = 2.0 V.Input buffer is 1.8-V tolerant.
An external 250-Ω pull-up resistor is not required, but recommended if signal levels on the board are not optimal.
For JTAG chains, the TDO pin of the first device drives the TDI pin of the second device in the chain. The VCCSEL input on the JTAG input I/O cells (TCK, TMS, TDI, and TRST) is internally hardwired to GND selecting the 3.3-V/2.5-V input buffer powered by VCCPD. The ideal case is to have the VCCIO of the TDO bank from the first device match the VCCSEL settings for TDI on the second device, but that may not be possible depending on the application. Table2–37 contains board design recommendations to ensure proper JTAG chain operation.
Table2–37.Supported TDO/TDI Voltage Combinations (Part 1 of2)Device
TDI Input Buffer Power
Stratix II GX TDO VCCIO Voltage Level in I/O Bank 4
VCCIO = 3.3 V
v (1)
VCCIO = 2.5 V
v (2)
VCCIO = 1.8 VVCCIO = 1.5 VVCCIO = 1.2 V
v (3)
Level shifter required
Level shifter required
StratixII GXAlways
VCCPD (3.3 V)
Stratix II GX Device Handbook, Volume 1
High-Speed Differential I/O with DPA Support
Table2–37.Supported TDO/TDI Voltage Combinations (Part 2 of2)Device
TDI Input Buffer Power
Stratix II GX TDO VCCIO Voltage Level in I/O Bank 4
VCCIO = 3.3 V
v (1)v (1), (4)v (1), (4)v (1), (4)
VCCIO = 2.5 V
v (2)v (2)v (2), (5)v (2), (5)
VCCIO = 1.8 VVCCIO = 1.5 VVCCIO = 1.2 V
v (3)v (3)vv (6)
Level shifter requiredLevel shifter requiredLevel shifter required
Level shifter requiredLevel shifter requiredLevel shifter required
Non-VCC = 3.3 V
StratixII GX
VCC = 2.5 VVCC = 1.8 VVCC = 1.5 V
Notes to Table2–37:(1)(2)(3)(4)(5)(6)
vv
The TDO output buffer meets VOH (MIN) = 2.4 V.The TDO output buffer meets VOH (MIN) = 2.0 V.
An external 250-Ω pull-up resistor is not required, but recommended if signal levels on the board are not optimal.Input buffer must be 3.3-V tolerant.Input buffer must be 2.5-V tolerant.Input buffer must be 1.8-V tolerant.
High-Speed Differential I/O with DPA Support
Stratix II GX devices contain dedicated circuitry for supporting
differential standards at speeds up to 1 Gbps. The LVDS differential I/O standards are supported in the Stratix II GX device. In addition, the
LVPECL I/O standard is supported on input and output clock pins on the top and bottom I/O banks.
The high-speed differential I/O circuitry supports the following high-speed I/O interconnect standards and applications:
■■■
SPI-4 Phase 2 (POS-PHY Level 4)SFI-4
Parallel RapidIO standard
There are two dedicated high-speed PLLs in the EP2SGX30 device and four dedicated high-speed PLLs in the EP2SGX60, EP2SGX90, and EP2SGX130 devices to multiply reference clocks and drive high-speed differential SERDES channels.
Tables2–38 through 2–41 show the number of channels that each Fast PLL can clock in each of the Stratix II GX devices. In Tables2–38 through 2–41, the first row for each transmitter or receiver provides the number of channels driven directly by the PLL. The second row below it shows the maximum channels a Fast PLL can drive if cross bank channels are used from the adjacent center Fast PLL. For example, in the 780-pin FineLineBGA EP2SGX30 device, PLL 1 can drive a maximum of
Stratix II GX Device Handbook, Volume 1
FPGA可编程逻辑器件芯片EP1S25F780C8中文规格书 - 图文
