Configuration Packets
Table 5-30:Configuration Registers (Cont’d)
R/WR/WR/WWRR/WW
Address6'h1d6'h1e6'h1f6'h206'h216'h22
Description
SEU frequency, enable and status.Expected readback signature for SEU detection.
Readback signature for readback command and SEU.
Boot History Register.
Mask pins for Multi-Pin Wake-Up.Initial CBC Value Register.
Register NameSEU_OPTEXP_SIGNRDBK_SIGNBOOTSTSEYE_MASKCBC_REG
CRC Register
The Cyclic Redundancy Check register utilizes a standard 32-bit CRC checksum algorithm to verify bitstream integrity during configuration. If the value written matches the current calculated CRC, the CRC_ERROR flag is cleared and startup is allowed.
FAR_MAJ Register
Frame Address Register sets the starting block and column address for the next configuration data input. See Table5-31.Table 5-31:
Frame Address Register (MAJOR)
BLK
Bits
[15:12]0xxx
ROW[11:8]xxxx
MAJOR[7:0]xxxxxxxx
FAR_MIN Register
Table 5-32:Frame Address Register (MINOR)
Block RAM
(Reserved)[13:10]0000
MINOR[9:0]xxxxxxxxxx
Bits[15:14]xx
There are three types of write to FAR: ???
Write one word to FAR_MAJ: only updates the FAR_MAJ.Write one word to FAR_MIN: only updates the FAR_MIN.
Write two words to FAR_MAJ: updates both FAR_MAJ and FAR_MIN; the data forFAR_MAJ will come first.
FDRI Register
Configuration data is written to the device by loading the command register with the WCFG command and then loading the Frame Data Input Register.
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2019
Chapter 5:Configuration Details
Configuration Watchdog Timer Register
The configuration watchdog timer (CWDT) register stores the value of the number of clock cycles that the FPGA will wait before the watchdog time-out (in which SYNCWORD is not received). The default is 64k clock cycles. The minimum value is 16h'0201.Table 5-39:
Bits[15:0]
CWDT Register
Value16h'ffff
HC_OPT_REG Register
The HC_OPT_REG register can only be reset to default by por_b.Table 5-40:
NameINIT_SKIPRESERVED
HC_OPT_REG Description
Bits65:0
Description
0: Do not skip initialization.1: Skip initialization.Reserved.
Default0011111
GENERAL Registers 1, 2, 3, 4, and 5
GENERAL1 and GENERAL2 registers are used to store loadable multiple configuration addresses for SPI and BPI.
GENERAL3 and GENERAL4 registers have a similar function as GENERAL1 and
GENERAL2, except that GENERAL3 and GENERAL4 store the golden bitstream address instead of the MultiBoot address.
The GENERAL5 register is a 16-bit register that allows users to store and access any extra information desired for the fail-safe scheme. These register contents are untouched during a soft reboot.
These registers are set by the bitstream. BitGen can be instructed not to write to these registers using the -g next_config_register_write:Disable command. This allows the ability to store user data in the FPGA between re-configuration attempts.Table 5-41:
NameGENERAL1GENERAL2GENERAL3GENERAL4GENERAL5
General Registers
Bits[15:0][15:0][15:0][15:0][15:0]
Description
The lower half of the multiple boot address.15:8 – SPI opcode.
7:0 – Higher half of the boot address.
The lower half of the golden bitstream address.15:8 – SPI opcode.
7:0 – Higher half of the golden boot address.The user-defined scratchpad register.
If the second configuration needs a previously unknown SPI vendor command, the new vendor command has already been loaded in GENERAL2 from the bitstream by this point.
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2019
Chapter 6:Readback and Configuration Verification
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2019
Chapter 7:Reconfiguration and MultiBoot
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2019
Chapter 8:Readback CRC
Because JTAG has the highest priority in the configuration mode, it takes over the
configuration bus whenever it needs to. The JTAG Instruction Register must not be parked at the CFG_IN, CFG_OUT, or ISC_ENABLE instructions.
Post_CRC Constraints
There are several Spartan-6 FPGA constraints used for signaling SEU events. All constraints have the same propagation rule. They are placed as an attribute on the CONFIG block, then propagated to the physical design object.
POST_CRC
POST_CRC enables the readback CRC feature in the FPGA. It uses the
POST_CRC_INTERNAL primitive's CRCERROR pin for signaling SEU events. By default, INIT is reserved as an SEU CRC error indicator but can be disabled by setting the POST_CRC_INIT_FLAG constraint.
The POST_CRC constraint is the best way to convey this information. It attaches to the CONFIG constraint. POST_CRC can be used by PAR and BitGen to reserve the INIT pin by not programming the IOB to drive the INIT pin.POST_CRC can take two values: ??
ENABLE
SEU detection is enabled.DISABLE
SEU detection is disabled.
POST_CRC_INIT_FLAG
POST_CRC_INIT_FLAG determines whether the Spartan-6 FPGA INIT_B pin is a source of the SEU error signal. Whether or not the INIT_B pin is used as the error signal, it cannot be used as user I/O when POST_CRC is enabled.
During configuration, the INIT pin operates normally. After configuration, if SEU analysis is enabled and INIT is reserved, the INIT pin (default) serves as an SEU status pin. An SEU is detected when a comparison of the real-time computed CRC differs from the pre-computed CRC, the CRCERROR pin is driven High, and the INIT pin is driven Low.POST_CRC_INIT_FLAG is used to disable the INIT_B pin from acting as the readback CRC error status output pin. The error condition is still available from the POST_CRC_INTERNAL site.
POST_CRC_INIT_FLAG can take two values:??
ENABLE
The INIT_B pin is used as an indicator of the SEU error signal (default).
DISABLE
INIT_B is not used as an indicator of the SEU error signal. The error condition is onlyavailable via POST_CRC_INTERNAL primitive.
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2019
FPGA可编程逻辑器件芯片XC2V80-6FF1517I中文规格书 - 图文
