DS099 (v3.1) June 27, 2013Product Specification
Introduction
The Spartan?-3 family of Field-Programmable Gate Arrays is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. The
eight-member family offers densities ranging from 50,000 to 5,000,000 system gates, as shown in Table1.
The Spartan-3 family builds on the success of the earlier Spartan-IIE family by increasing the amount of logic
resources, the capacity of internal RAM, the total number of I/Os, and the overall level of performance as well as by improving clock management functions. Numerous enhancements derive from the Virtex?-II platform technology. These Spartan-3 FPGA enhancements,
combined with advanced process technology, deliver more functionality and bandwidth per dollar than was previously possible, setting new standards in the programmable logic industry.
Because of their exceptionally low cost, Spartan-3 FPGAs are ideally suited to a wide range of consumer electronics applications, including broadband access, home networking, display/projection and digital television equipment.
The Spartan-3 family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial cost, the lengthy development cycles, and the inherent inflexibility of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary, an impossibility with ASICs.
Table 1:Summary of Spartan-3 FPGA Attributes
DeviceXC3S50(2)XC3S200(2)XC3S400(2)XC3S1000(2)XC3S1500XC3S2000XC3S4000XC3S5000
CLB Array
(One CLB = Four Slices)System Equivalent
GatesLogic Cells(1)Total
RowsColumns
CLBs 50K200K400K1M1.5M2M4M5M
1,7284,3208,06417,28029,95246,08062,20874,880
16243248648096104
1220284052647280
1924808961,9203,3285,1206,9128,320
Features
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Low-cost, high-performance logic solution for high-volume,consumer-oriented applications?Densities up to 74,880 logic cellsSelectIO? interface signaling?Up to 633 I/O pins?622+ Mb/s data transfer rate per I/O?18 single-ended signal standards?8 differential I/O standards including LVDS, RSDS?Termination by Digitally Controlled Impedance?Signal swing ranging from 1.14V to 3.465V?Double Data Rate (DDR) support?DDR, DDR2 SDRAM support up to 333Mb/sLogic resources?Abundant logic cells with shift register capability?Wide, fast multiplexers?Fast look-ahead carry logic?Dedicated 18 x 18 multipliers?JTAG logic compatible with IEEE 1149.1/1532SelectRAM? hierarchical memory?Up to 1,872 Kbits of total block RAM?Up to 520 Kbits of total distributed RAMDigital Clock Manager (up to four DCMs)?Clock skew elimination?Frequency synthesis?High resolution phase shifting
Eight global clock lines and abundant routing
Fully supported by Xilinx ISE? and WebPACK? softwaredevelopment systems
MicroBlaze? and PicoBlaze? processor, PCI?,PCIExpress? PIPE Endpoint, and other IP coresPb-free packaging options
Automotive Spartan-3 XA Family variant
?
??
?????
Distributed Block
Dedicated
RAM Bits RAM Bits DCMs
Multipliers
(K=1024)(K=1024)
12K30K56K120K208K320K432K520K
72K216K288K432K576K720K1,728K1,872K
4121624324096104
24444444
Maximum
Max.
Differential
User I/O
I/O Pairs124173264391487565633633
5676116175221270300300
Notes:
1.2.Logic Cell = 4-input Look-Up Table (LUT) plus a ‘D’ flip-flop. \otal CLBs\These devices are available in Xilinx Automotive versions as described in DS314: Spartan-3 Automotive XA FPGA Family.DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Functional Description
Table 13:Block RAM Port Signals (Cont’d)
Signal DescriptionData Output Bus
Port A Port B Signal NameSignal Name
DOA
DOB
DirectionOutput
Function
Basic data access occurs whenever WE is inactive. The DO outputs mirror the data stored in the addressed memory location.
Data access with WE asserted is also possible if one of the following two attributes is chosen: WRITE_FIRST and READ_FIRST. WRITE_FIRST simultaneously presents the new input data on the DO output port and writes the data to the address RAM location. READ_FIRST presents the previously stored RAM data on the DO output port while writing new data to RAM.
A third attribute, NO_CHANGE, latches the DO outputs upon the assertion of WE.
It is possible to configure a port’s total data path width (w) to be 1, 2, 4, 9, 18, or 36 bits. This selection applies to both the DI and DO paths. See the DI signal description.
Parity inputs represent additional bits included in the data input path to support error detection. The number of parity bits \(same as for the DO bus) depends on a port’s total data path width (w). See Table14.
When asserted together with EN, this input enables the writing of data to the RAM. In this case, the data access attributes WRITE_FIRST, READ_FIRST or NO_CHANGE determines if and how data is updated on the DO outputs. See the DO signal description.
When WE is inactive with EN asserted, read operations are still possible. In this case, a transparent latch passes data from the addressed memory location to the DO outputs.
When asserted, this input enables the CLK signal to synchronize Block RAM functions as follows: the writing of data to the DI inputs (when WE is also asserted), the updating of data at the DO outputs as well as the setting/resetting of the DO output latches.
When de-asserted, the above functions are disabled.
When asserted, this pin forces the DO output latch to the value that the SRVAL attribute is set to. A Set/Reset operation on one port has no effect on the other ports functioning, nor does it disturb the memory’s data contents. It is synchronized to the CLK signal.
This input accepts the clock signal to which read and write operations are synchronized. All associated port inputs are required to meet setup times with respect to the clock signal’s active edge. The data output bus responds after a clock-to-out delay referenced to the clock signal’s active edge.
Parity Data Output(s)
DOPADOPBOutput
Write EnableWEAWEBInput
Clock EnableENAENBInput
Set/ResetSSRASSRBInput
ClockCLKACLKBInput
Port Aspect Ratios
On a given port, it is possible to select a number of different possible widths (w – p) for the DI/DO buses as shown in
Table14. These two buses always have the same width. This data bus width selection is independent for each port. If the data bus width of Port A differs from that of Port B, the Block RAM automatically performs a bus-matching function. When data are written to a port with a narrow bus, then read from a port with a wide bus, the latter port will effectively combine “narrow” words to form “wide” words. Similarly, when data are written into a port with a wide bus, then read from a port with a narrow bus, the latter port will divide “wide” words to form “narrow” words. When the data bus width is eight bits or greater, extra parity bits become available. The width of the total data path (w) is the sum of the DI/DO bus width and any parity bits (p).
The width selection made for the DI/DO bus determines the number of address lines according to the relationship expressed below:
r = 14 – [log(w–p)/log(2)]
Equation1
In turn, the number of address lines delimits the total number (n) of addressable locations or depth according to the following equation:
n = 2r
DS099 (v3.1) June 27, 2013Product Specification
Equation2
Spartan-3 FPGA Family: Functional Description
The product of w and n yields the total block RAM capacity. Equation1 and Equation2 show that as the data bus width increases, the number of address lines along with the number of addressable memory locations decreases. Using the permissible DI/DO bus widths as inputs to these equations provides the bus width and memory capacity measures shown in Table14.
Table 14:Port Aspect Ratios for Port A or B
DI/DO Bus Width(w – p Bits)
12481632
DIP/DOP Bus Width (p Bits)
000124
Total Data Path Width (w Bits)
12491836
ADDR Bus Width
(r Bits)
14131211109
No. of Addressable Block RAM Locations (n)Capacity (Bits)
16,3848,1924,0962,0481,024512
16,38416,38416,38418,43218,43218,432
Block RAM Data Operations
Writing data to and accessing data from the block RAM are synchronous operations that take place independently on each
of the two ports.
The waveforms for the write operation are shown in the top half of the Figure15, Figure16, and Figure17. When the WE and EN signals enable the active edge of CLK, data at the DI input bus is written to the block RAM location addressed by the ADDR lines.
There are a number of different conditions under which data can be accessed at the DO outputs. Basic data access always occurs when the WE input is inactive. Under this condition, data stored in the memory location addressed by the ADDR lines passes through a transparent output latch to the DO outputs. The timing for basic data access is shown in the portions of Figure15, Figure16, and Figure17 during which WE is Low.
X-Ref Target - Figure 15DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Functional Description
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Phase Shifting: The DCM provides the ability to shift the phase of all its output clock signals with respect to its inputclock signal.
The DCM has four functional components: the Delay-Locked Loop (DLL), the Digital Frequency Synthesizer (DFS), the Phase Shifter (PS), and the Status Logic. Each component has its associated signals, as shown in Figure19.
X-Ref Target - Figure 19DCMPSINCDECPSENPSCLKPhaseShifterPSDONEOutput StageCLKINInput StageDelay TapsCLK0CLK90CLK180CLK270CLK2XCLK2X180CLKDVCLKFXCLKFX1808ClockDistributionDelayCLKFBDFSDLLRSTStatusLogicLOCKEDSTATUS [7:0]DS099-2_07_040103Figure 19:DCM Functional Blocks and Associated Signals
Delay-Locked Loop (DLL)
The most basic function of the DLL component is to eliminate clock skew. The main signal path of the DLL consists of an input stage, followed by a series of discrete delay elements or taps, which in turn leads to an output stage. This path together with logic for phase detection and control forms a system complete with feedback as shown in Figure20.
X-Ref Target - Figure 20CLKINDelay1Delay2Delayn-1DelaynCLK0CLK90CLK180CLK270CLK2XCLK2X180CLKDVControlOutput SectionLOCKEDCLKFBRSTPhaseDetectionDS099-2_08_041103Figure 20:Simplified Functional Diagram of DLL
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Functional Description
The DLL component has two clock inputs, CLKIN and CLKFB, as well as seven clock outputs, CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV as described in Table16. The clock outputs drive simultaneously; however, the High Frequency mode only supports a subset of the outputs available in the Low Frequency mode. See DLL Frequency Modes, page35. Signals that initialize and report the state of the DLL are discussed in The Status Logic Component, page41.
Table 16:DLL Signals
Mode Support
SignalCLKINCLKFBCLK0CLK90CLK180CLK270CLK2XCLK2X180CLKDV
DirectionInputInputOutputOutputOutputOutputOutputOutputOutput
Accepts original clock signal.
Description
Low Frequency
YesYesYesYesYesYesYesYesYes
High Frequency
YesYesYesNoYesNoNoNoYes
Accepts either CLK0 or CLK2X as feed back signal. (Set CLK_FEEDBACK attribute accordingly).
Generates clock signal with same frequency and phase as CLKIN.
Generates clock signal with same frequency as CLKIN, only phase-shifted 90°.Generates clock signal with same frequency as CLKIN, only phase-shifted 180°.Generates clock signal with same frequency as CLKIN, only phase-shifted 270°.Generates clock signal with same phase as CLKIN, only twice the frequency.Generates clock signal with twice the frequency of CLKIN, phase-shifted 180° with respect to CLKIN.
Divides the CLKIN frequency by CLKDV_DIVIDE value to generate lower frequency clock signal that is phase-aligned to CLKIN.
The clock signal supplied to the CLKIN input serves as a reference waveform, with which the DLL seeks to align the
feedback signal at the CLKFB input. When eliminating clock skew, the common approach to using the DLL is as follows: The CLK0 signal is passed through the clock distribution network to all the registers it synchronizes. These registers are either internal or external to the FPGA. After passing through the clock distribution network, the clock signal returns to the DLL via a feedback line called CLKFB. The control block inside the DLL measures the phase error between CLKFB and CLKIN. This phase error is a measure of the clock skew that the clock distribution network introduces. The control block activates the appropriate number of delay elements to cancel out the clock skew. Once the DLL has brought the CLK0 signal in phase with the CLKIN signal, it asserts the LOCKED output, indicating a “lock” on to the CLKIN signal.
DLL Attributes and Related Functions
A number of different functional options can be set for the DLL component through the use of the attributes described in Table17. Each attribute is described in detail in the sections that follow:Table 17:DLL Attributes
Attribute
CLK_FEEDBACK
DLL_FREQUENCY_MODE CLKIN_DIVIDE_BY_2CLKDV_DIVIDE
Description
Chooses between High Frequency and Low Frequency modesHalves the frequency of the CLKIN signal just as it enters the DCM Selects constant used to divide the CLKIN input frequency to generate the CLKDV output frequency
Enables 50% duty cycle correction for the CLK0, CLK90, CLK180, and CLK270 outputs
Values
LOW, HIGH TRUE, FALSE
1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6.0, 6.5, 7.0, 7.5, 8, 9, 10, 11, 12, 13, 14, 15, and 16.TRUE, FALSE
Chooses either the CLK0 or CLK2X output to drive the CLKFB inputNONE, 1X, 2X
DUTY_CYCLE_CORRECTION
DS099 (v3.1) June 27, 2013Product Specification
FPGA可编程逻辑器件芯片XCZU9EG-2FFVC900E中文规格书 - 图文
