Chapter 5:DSP Blocks in StratixIII Devices
DSP Block Resource Descriptions
Shift registers are useful in DSP functions such as FIR filters. When implementing 18×18 or smaller width multipliers, you do not need external logic to create the shift register chain because the input shift registers are internal to the DSP block. This implementation significantly reduces the logical element (LE) resources required, avoids routing congestion, and results in predictable timing.
The first multiplier in every half DSP block (top- and bottom-half) in StratixIII
devices has a multiplexer for the first multiplier B-input (lower-leg input) register to select between general routing and loopback, as shown in Figure5–6. In loopback mode, the most significant 18-bit registered outputs are connected as feedback to the multiplier input of the first top multiplier in each half DSP block. Loopback modes are used by recursive filters where the previous output is needed to compute the current output.
The loopback mode is described in detail in “Two-Multiplier Adder Sum Mode” on page5–21.
Table5–3 lists the input register modes for the DSP block.
Table5–3.Input Register Modes Register Input Mode (1)Parallel inputShift register input (2)Loopback input (3)Notes to Table5–3:
(1)The multiplier operand input wordlengths are statically configured at compile time.(2)Available only on the A-operand.
(3)Only one loopback input is allowed per Half-Block. See Figure5–15 for details.
9×9v——12×12v——18×18vvv36×36v——Doublev——Multiplier and First-Stage Adder
The multiplier stage natively supports 9×9, 12×12, 18×18, or 36×36 multipliers. Other wordlengths are padded up to the nearest appropriate native wordlength; for example, 16×16 would be padded up to use 18×18. Refer to “Independent
Multiplier Modes” on page5–15 for more details. Depending on the data width of the multiplier, a single DSP block can perform many multiplications in parallel.
Each multiplier operand can be a unique signed or unsigned number. Two dynamic signals, signa and signb, control the representation of each operand, respectively. A logic1 value on the signa/signb signal indicates that data A/data B is a signed number; a logic0 value indicates an unsigned number. Table5–4 lists the sign of the multiplication result for the various operand sign representations. The result of the multiplication is signed if any one of the operands is a signed value.
Table5–4.Multiplier Sign Representation
Data A (signa Value)Unsigned (logic0)Unsigned (logic0)Signed (logic1)Signed (logic1)Data B (signb Value)Unsigned (logic0)Signed (logic1)Unsigned (logic0)Signed (logic1)ResultUnsignedSignedSignedSignedStratix III Device Handbook, Volume 1
Chapter 5:DSP Blocks in StratixIII DevicesOperational Mode Descriptions
Four-Multiplier Adder
In the four-multiplier adder configuration shown in Figure5–17, the DSP block can implement two four-multiplier adders (one four-multiplier adder per half DSP block). These modes are useful for implementing one-dimensional and two-dimensional filtering applications. The four-multiplier adder is performed in two addition stages. The outputs of two of the four multipliers are initially summed in the two first-stage adder blocks. The results of these two adder blocks are then summed in the
second-stage adder block to produce the final four-multiplier adder result, as shown by Equation5–2 and Equation5–3.
Figure5–17.Four-Multiplier Adder Mode for Half-DSP Block
clock[3..0]ena[3..0]aclr[3..0]signasignboutput_roundoutput_saturateoverflowdataa_0[ ]
datab_0[ ]
+dataa_1[ ]
Pipeline Register Bankdatab_1[ ]dataa_2[ ]
+Output Register BankInput Register BankRound/Saturateresult[ ]
datab_2[ ]
+dataa_3[ ]
datab_3[ ]
Half-DSP BlockThe four-multiplier adder mode supports the round and saturation logic unit. You can use the pipeline registers and output registers within the DSP block to pipeline the multiplier-adder result, increasing the performance of the DSP block.
Stratix III Device Handbook, Volume 1
Chapter 6:Clock Networks and PLLs in StratixIII Devices
Clock Networks in StratixIII Devices
Table6–4.Clock Input Pin Connectivity to Regional Clock Networks (Quadrant 2) (Part 2 of 2)Clock Resource0RCLK50RCLK51RCLK52RCLK53————1————2————3————4————5————6————CLK (p/n Pins)7————8————9————10————11————12—v——13v———14———v15——v—Table6–5 lists the connectivity between the dedicated clock input pins and RCLKs in device Quadrant 3. A given clock input pin can drive two adjacent regional clock networks to create a dual-regional clock network.
Table6–5.Clock Input Pin Connectivity to Regional Clock Networks (Quadrant 3)Clock Resource0RCLK22RCLK23RCLK24RCLK25RCLK26RCLK27RCLK28RCLK29RCLK30RCLK31RCLK32RCLK33RCLK34RCLK35RCLK36RCLK37————————————————1————————————————2————————————————3————————————————4—v———v———v——————5v———v———v———————6———v———v————————CLK (p/n Pins)7——v———v—————————8—————————————v——9————————————v———10———————————v———v11——————————v———v—12————————————————13————————————————14————————————————15————————————————Stratix III Device Handbook, Volume 1
FPGA可编程逻辑器件芯片EP3C55F484C8中文规格书
