Chapter1
Introduction to the RocketIO GTX Transceiver
Overview
The RocketIO? GTX transceiver is a power-efficient transceiver for Virtex?-5 FPGAs. The GTX transceiver is highly configurable and tightly integrated with the programmable logic resources of the FPGA. It provides the following features to support a wide variety of applications:???
Current Mode Logic (CML) serial drivers/buffers with configurable termination,voltage swing, and coupling.
Programmable TX pre-emphasis, RX equalization, and linear and decision feedbackequalization (DFE) for optimized signal integrity.
Line rates from 750Mb/s to 6.5Gb/s, with optional 5x digital oversampling requiredfor rates between 150Mb/s and 750Mb/s. The nominal operation range of the sharedPMA PLL is from 1.5GHz to 3.25GHz. These are nominal values, see DS202: Virtex-5FPGA Data Sheet for specifications.
Optional built-in PCS features, such as 8B/10B encoding, comma alignment, channelbonding, and clock correction.
Fixed latency modes for minimized, deterministic datapath latency.
Beacon signaling for PCI Express? designs and Out-of-Band signaling includingCOM signal support for SATA designs.
RX/TX Gearbox provides header insertion and extraction support for 64B/66B and64B/67B (Interlaken) protocols.Receiver eye scan:
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Vertical eye scan in the voltage domain for testing purposesHorizontal eye scan in the time domain for testing purposes
The first-time user is recommended to read High-Speed Serial I/O Made Simple [Ref1], which discusses high-speed serial transceiver technology and its applications.
Table1-1 lists some of the standard protocols designers can implement using the GTX transceiver. The Xilinx? CORE Generator? tool includes a Wizard to automatically configure GTX transceivers to support one of these protocols or perform custom configuration (see Chapter2, “RocketIO GTX Transceiver Wizard”).
The GTX_DUAL tile offers a data rate range and features that allow physical layer support for various protocols as illustrated in Table1-1.
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
Chapter 1:Introduction to the RocketIO GTX Transceiver
Table 1-1:List of Standards Supported by the GTX_DUAL Tile
Data Rates2.5Gb/s5.0Gb/s
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Miscellaneous Features
TX receive detect
Loss of Signal (LOS)/Idle state detectLow power statesBeacon signaling
Ground referenced termination
Compatible ProtocolsPCI Express, Rev. 1.0a PCI Express, Rev. 1.1PCI Express, Rev. 2.0
Interlaken
XAUI 802.3ae D5p0OIF-CEI6GOC-12/48
3.125Gb/s, 6.25Gb/s
3.125Gb/s6.25Gb/s622.08/2488.32Mb/s
Header insertion/extraction for 64B/67BLOS
?No Equalizer (EQ), low power mode?4-tap adaptive DFE
?Allows FIFO bypassing for synchronousoperation
?5x digital oversampling
Rate negotiation (allows operating the TX and RX at different speeds)
FC-1, Revision 4.0 FC-2, Revision 4.0FC-4, Revision 4.010GFCSDIHD-SDIDVB-ASI3G-SDI
10G Base-CX4 802.3ak/D4.0Gigabit Ethernet (1000BASE-CX 802.3z/D5.0)
SATA Generation 1/2, Rev. 1.0aSATA Generation 2, Rev. 1.0a
1.0625Gb/s2.125Gb/s4.25Gb/s3.1875Gb/s176/270/360Mb/s1.485/1.4835Gb/s
270Mb/s2.970Gb/s3.125Gb/s1.25Gb/s1.5Gb/s3.0Gb/s
?Rate negotiation for Generation 2 (entire linkoperates at Generation 1/Generation 2 speeds)?LOS
?OOB beacon5x digital oversampling
Serial RapidIOCPRI, Version 2.0
Infiniband, Volume 2, Release 1.1SFI-5
OBSAI RP3, Spec. Issue 1.0Aurora
1.25/2.5/3.125/6.25Gb/s614.4/1228.8/2457.6Mb/s
2.5Gb/s2.488 – 3.125Gb/s768/1536/3072Mb/s150Mb/s – 6.5Gb/s
Synchronous clocking (bypass FIFOs)5x digital oversampling
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
Section 1: FPGA Level Design
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
Chapter 1:Introduction to the RocketIO GTX Transceiver
Figure1-3 shows a diagram of a GTX_DUAL tile, containing two GTX transceivers and a shared resources block. The GTX_DUAL tile is the HDL primitive used to operate GTX transceivers in the FPGA.
X-Ref Target - Figure 1-3GTX_DUAL TilePackage PinsMGTTXP0MGTTXN0TXP0TXN0GTX TXTX-PMAGTX0FPGA PinsData From FPGA6TX-PCSTXDATA0[31:0]TXBYPASS8B10B0[3:0]TXCHARISK0[3:0]TXCHARDISPMODE0[3:0]TXCHARDISPVAL0[3:0]RXPOWERDOWN0[1:0]RXSTATUS0[2:0]RXDATA0[31:0]Data To FPGAMGTRXP0MGTRXN0RXP0RXN0GTX RX7RX-PMARX-PCSShared ResourcesRXDISPERR0[3:0]RXCHARISCOMMA0[3:0]RXCHARISSK0[3:0]RXRUNDISP0[3:0]RXVALID0[1:0]TXOUTCLK0TXUSRCLK0TXUSRCLK20RXUSRCLK0RXUSRCLK20RXRECCLK0CLKIN(1)DRPTXOUTCLK1TXUSRCLK1TXUSRCLK21RXUSRCLK1RXUSRCLK21RXRECCLK1MGTAVTTTXMGTAVTTRXMGTAVTTTXAVTTTXAVTTRXAVTTTX1SharedPMAPLLPLL LockDetection2ResetControlMGTAVCCMGTAVCCPLLMGTAVCCAVCCAVCCPLLAVCC3ClockingPowerControl45GTX1MGTTXP1MGTTXN1TXP1TXN1GTX TXTX-PMAData From FPGA6TXDATA1[31:0]TXBYPASS8B10B1[3:0]TXCHARISK1[3:0]TXCHARDISPMODE1[3:0]RXPOWERDOWN1[1:0]RXSTATUS1[2:0]RXDATA1[31:0]TX-PCSData To FPGAMGTRXP1MGTRXN1RXP1RXN1GTX RX7RX-PMARX-PCSRXDISPERR1[3:0]RXCHARISCOMMA1[3:0]RXCHARISSK1[3:0]RXVALID1[1:0]UG198_c1_02_010308Notes:
1.CLKIN is a simplification for a clock source. See Figure5-3, page97 for details on CLKIN.
Figure 1-3:GTX_DUAL Tile Block Diagram
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
FPGA可编程逻辑器件芯片XC2S200-5CSG144I中文规格书 - 图文
