Boundary-Scan and JTAG Configuration
Introduction
Spartan?-6 devices support IEEE Std 1149.1, defining Test Access Port (TAP) and
boundary-scan architecture. These standards ensure the board-level integrity of individual components and the interconnections between them. In addition to connectivity testing, boundary-scan architecture offers flexibility for vendor-specific instructions, such as configure and verify, which add the capability of loading configuration data directly to FPGAs and compliant memories. TAP and boundary-scan architecture is commonly referred to collectively as JTAG.
Boundary-Scan for Spartan-6 Devices Using IEEE Std 1149.1
The Spartan-6 family is fully compliant with the IEEE Std 1149.1 (TAP and boundary-scan architecture). The architecture includes all mandatory elements defined in IEEE Std 1149.1. These elements include the TAP, the TAP controller, the Instruction register, the instruction decoder, the boundary-scan register, and the BYPASS register. The Spartan-6 family also supports a 32-bit Identification register in full compliance with the standard. Outlined in the following sections are the details of the JTAG architecture for Spartan-6 devices. More details about the JTAG architecture for Spartan-6devices can be found in Chapter10, Advanced JTAG Configurations.
Test Access Port (TAP)
The Spartan-6 FPGA TAP contains four mandatory dedicated pins as specified by the protocol in Spartan-6 devices and in typical JTAG architecture (see Figure10-1, page162). Three input pins and one output pin control the IEEE Std 1149.1 boundary-scan TAP controller. Optional control pins, such as Test Reset (TRST), and enable pins might be found on devices from other manufacturers. It is important to be aware of these optional signals when interfacing Xilinx devices with parts from different vendors because they might need to be driven.
The IEEE Std 1149.1 boundary-scan TAP controller is a state machine (16 states), shown in Chapter10, Advanced JTAG Configurations.
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2019
Chapter 5:Configuration Details
CCLK_FREQ Register
Table 5-45:
NameEXT_MCLK
Master Mode CCLK Frequency Select Description
Bits14
Description
Select external master clock.0: Select internal master clock.1: Select external master clock.
CCLK frequency select. This register is a shared use register with the ExtMCCLK_Divide signal, which divides the external clock.
Default0
MCLK_FREQ9:010x1BE
PU_GWE Register
This 10-bit register stores the wake-up GWE sequence from suspend. See Table5-46.Table 5-46:
Wake-Up 10-Bit Register Default
[9:0]10h'006
BitsDefault Value
PU_GTS Register
This 10-bit register stores the wake-up GTS sequence from suspend. See Table5-47.Table 5-47:
10-Bit Wake-Up Register Default
[9:0]10h'005
BitsDefault Value
Boot History Status Register (BOOTSTS)
This register is reset by POR or asserting PROGRAM_B. It is not reset by an IPROG
command, because the purpose of this register is to store the potential errors of a MultiBoot operation. At EOS or an error condition, status (_0) is updated with the current status. If fallback or MultiBoot occurs, status (_1) is updated at EOS or an error condition. BOOTSTS is not updated after a successful IPROG command. The name of each bit position in the BOOTSTS register is given in Table5-48.Table 5-48:
NameSTRIKE_CNTCRC_ERROR_1ID_ERROR_1WTO_ERROR_1RESERVEDFALLBACK_1VALID_1
BOOTSTS Register Description
Bits15:1211109876
Strike count. CRC error.
IDCODE not validated while trying to write FDRI.Watchdog time-out error.Reserved.
1: Fallback to 00 address.0: Normal configuration.Status Valid.
Description
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2019
Configuration Packets
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2019
Chapter 6:Readback and Configuration Verification
Readback Command Sequences
Spartan-6 FPGA configuration memory is read from the FDRO (Frame Data Register - Output) configuration register and can be accessed from the JTAG, SelectMAP, and ICAP interfaces. For the JTAG and SelectMAP interfaces, readback is possible while the FPGA design is active or in a shutdown state, although block RAMs cannot be accessed by the user design while they are being accessed by the configuration logic.
Accessing Configuration Registers through the SelectMAP Interface
To read configuration memory through the SelectMAP interface, users must set the
interface for write control to send commands to the FPGA, and then switch the interface to read control to read data from the device. Write and read control for the SelectMAP
interface is determined by the RDWR_B input: the SelectMAP data pins are inputs when the interface is set for Write control (RDWR_B = 0); they are outputs when the interface is set for Read control (RDWR_B = 1).
The CSI_B signal must be deasserted (CSI_B =1) before toggling the RDWR_B signal, otherwise the user causes an abort (refer to SelectMAP ABORT, page157 for details). The procedure for changing the SelectMAP interface from Write to Read Control, or vice versa, is:1.2.
Deassert CSI_B.Toggle RDWR_B.
RDWR_B = 0: Write controlRDWR_B = 1: Read control3.4.5.
X-Ref Target - Figure 6-1Assert CSI_B.
CSI_B is synchronous to CCLK.
This procedure is illustrated in Figure6-1.
CSI_BRDWR_BWRITEREADByte nByte 0Byte nDATA[0:7]Byte 0CCLKUG380_c6_01_042909Figure 6-1:Changing the SelectMAP Port from Write to Read Control
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2019
Readback Command Sequences
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2019
FPGA可编程逻辑器件芯片XC2S30-6FGG456I中文规格书 - 图文
