FPGA可编程逻辑器件芯片EP2S30F672I5N中文规格书 - 图文

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SII51004-3.2

Stratix II

Hot-Socketing Specifications

4.Hot Socketing &Power-OnReset

Stratix? II devices offer hot socketing, which is also known as hot plug-in or hot swap, and power sequencing support without the use of any external devices. You can insert or remove a StratixII board in a system during system operation without causing undesirable effects to the running system bus or the board that was inserted into the system. The hot socketing feature also removes some of the difficulty when you use Stratix II devices on printed circuit boards (PCBs) that also contain a mixture of 5.0-, 3.3-, 2.5-, 1.8-, 1.5- and 1.2-V devices. With the StratixII hot socketing feature, you no longer need to ensure a proper power-up sequence for each device on the board.The StratixII hot socketing feature provides:

■Board or device insertion and removal without external components or board manipulation

■Support for any power-up sequence

■

Non-intrusive I/O buffers to system buses during hot insertion

This chapter also discusses the power-on reset (POR) circuitry in StratixII devices. The POR circuitry keeps the devices in the reset state until the VCC is within operating range.

Stratix II devices offer hot socketing capability with all three features listed above without any external components or special design requirements. The hot socketing feature in Stratix II devices allows:

■The device can be driven before power-up without any damage tothe device itself.

■

I/O pins remain tri-stated during power-up. The device does notdrive out before or during power-up, thereby affecting other buses in operation.

■

Signal pins do not drive the VCCIO, VCCPD, or VCCINT power supplies. External input signals to I/O pins of the device do not internallypower the VCCIO or VCCINT power supplies of the device via internalpaths within the device.

DC & Switching Characteristics

Table5–17.SSTL-18 Class II SpecificationsSymbol

VCCIOVREFVTT

Parameter

Output supply voltageReference voltageTermination voltage

ConditionsMinimum

1.710.855VREF – 0.04VREF + 0.125

Typical

1.800.900VREF

Maximum

1.890.945VREF + 0.04

Unit

VVVV

VIH (DC)High-level DC input voltageVIL (DC)Low-level DC input voltageVIH (AC)High-level AC input voltageVIL (AC)Low-level AC input voltageVOHVOL(1)

VREF – 0.125

VREF + 0.25

VREF – 0.25

IOH = –13.4 mA (1)IOL = 13.4 mA (1)

VCCIO – 0.28

0.28

VVVVV

High-level output voltageLow-level output voltage

Note to Table5–17:

This specification is supported across all the programmable drive settings available for this I/O standard as shown in the StratixII Architecture chapter in volume 1 of the StratixII Device Handbook.

Table5–18.SSTL-18 Class I & II Differential SpecificationsSymbol

VCCIOVSWING(DC)

Parameter

Output supply voltageDC differential input voltage

ConditionsMinimum

1.710.25(VCCIO/2) – 0.175

0.5

Typical

1.80

Maximum

1.89

Unit

VX (AC)AC differential input cross

point voltageVSWING(AC)VISOΔVISOVOX (AC)

AC differential input voltageInput clock signal offset voltage

Input clock signal offset voltage variation

AC differential cross point voltage

(VCCIO/2) + 0.175

0.5 × VCCIO

±200

(VCCIO/2) – 0.125

(VCCIO/2) + 0.125

VmVV

Stratix II Device Handbook, Volume 1

Operating Conditions

Table5–19.SSTL-2 Class I SpecificationsSymbol

VCCIOVTTVREFVIH (DC)VIL (DC)VIH (AC)VIL (AC)VOHVOL(1)

Parameter

Output supply voltageTermination voltageReference voltageHigh-level DC input voltageLow-level DC input voltageHigh-level AC input voltageLow-level AC input voltageHigh-level output voltageLow-level output voltage

ConditionsMinimum

2.375VREF – 0.041.188VREF + 0.18–0.30VREF + 0.35

Typical

2.500VREF1.250

Maximum

2.625VREF + 0.041.3133.00VREF – 0.18

Unit

VVVVVV

VREF - 0.35

IOH = –8.1 mA (1)IOL = 8.1 mA (1)

VTT + 0.57

VTT – 0.57

VVV

Note to Table5–19:

This specification is supported across all the programmable drive settings available for this I/O standard as shown in the StratixII Architecture chapter in volume 1 of the StratixII Device Handbook.

Table5–20.SSTL-2 Class II SpecificationsSymbol

VCCIOVTTVREFVIH (DC)VIL (DC)VIH (AC)VIL (AC)VOHVOL(1)

Parameter

ConditionsMinimum

2.375VREF – 0.041.188VREF + 0.18–0.30VREF + 0.35

Typical

2.500VREF1.250

Maximum

2.625VREF + 0.041.313VCCIO + 0.30VREF – 0.18

Unit

VVVVVV

VREF - 0.35

IOH = –16.4 mA (1)IOL = 16.4 mA (1)

VTT + 0.76

VTT – 0.76

VVV

Note to Table5–20:

This specification is supported across all the programmable drive settings available for this I/O standard as shown in the StratixII Architecture chapter in volume 1 of the StratixII Device Handbook.

Stratix II Device Handbook, Volume 1

Power Consumption

Stratix II Device Handbook, Volume 1

Timing Model

Stratix II Device Handbook, Volume 1