1Spartan-3 FPGA Family
Data Sheet
Product Specification
DS099 June 27, 2013
Module 1:
Introduction and Ordering Information
DS099 (v3.1) June 27, 2013??????
IntroductionFeatures
Architectural OverviewArray Sizes and ResourcesUser I/O ChartOrdering Information
Module 4: Pinout Descriptions
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Pin Descriptions?
Pin Behavior During ConfigurationPackage OverviewPinout Tables?
Footprints
Module 2: Functional Description
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Input/Output Blocks (IOBs)?????
IOB Overview
SelectIO? Interface I/O Standards
Configurable Logic Blocks (CLBs)Block RAMDedicated Multipliers
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Digital Clock Manager (DCM)Clock NetworkConfiguration
Module 3:
DC and Switching Characteristics
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DC Electrical Characteristics?????
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Absolute Maximum RatingsSupply Voltage SpecificationsRecommended Operating ConditionsDC CharacteristicsI/O Timing
Internal Logic TimingDCM Timing
Configuration and JTAG Timing
Switching Characteristics
DS099 June 27, 2013Product Specification
Spartan-3 FPGA Family:
Introduction and Ordering Information
DS099 (v3.1) June 27, 2013
Product Specification
Introduction
The Spartan?-3 family of Field-Programmable Gate Arrays is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. The
eight-member family offers densities ranging from 50,000 to 5,000,000 system gates, as shown in Table1.
The Spartan-3 family builds on the success of the earlier Spartan-IIE family by increasing the amount of logic
resources, the capacity of internal RAM, the total number of I/Os, and the overall level of performance as well as by improving clock management functions. Numerous enhancements derive from the Virtex?-II platform technology. These Spartan-3 FPGA enhancements,
combined with advanced process technology, deliver more functionality and bandwidth per dollar than was previously possible, setting new standards in the programmable logic industry.
Because of their exceptionally low cost, Spartan-3 FPGAs are ideally suited to a wide range of consumer electronics applications, including broadband access, home networking, display/projection and digital television equipment.
The Spartan-3 family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial cost, the lengthy development cycles, and the inherent inflexibility of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary, an impossibility with ASICs.
Table 1:Summary of Spartan-3 FPGA Attributes
DeviceXC3S50(2)XC3S200(2)XC3S400(2)XC3S1000(2)XC3S1500XC3S2000XC3S4000XC3S5000
CLB Array
(One CLB = Four Slices)System Equivalent
GatesLogic Cells(1)Total
RowsColumns
CLBs 50K200K400K1M1.5M2M4M5M
1,7284,3208,06417,28029,95246,08062,20874,880
16243248648096104
1220284052647280
1924808961,9203,3285,1206,9128,320
Features
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Low-cost, high-performance logic solution for high-volume,consumer-oriented applications?Densities up to 74,880 logic cellsSelectIO? interface signaling?Up to 633 I/O pins?622+ Mb/s data transfer rate per I/O?18 single-ended signal standards?8 differential I/O standards including LVDS, RSDS?Termination by Digitally Controlled Impedance?Signal swing ranging from 1.14V to 3.465V?Double Data Rate (DDR) support?DDR, DDR2 SDRAM support up to 333Mb/sLogic resources?Abundant logic cells with shift register capability?Wide, fast multiplexers?Fast look-ahead carry logic?Dedicated 18 x 18 multipliers?JTAG logic compatible with IEEE 1149.1/1532SelectRAM? hierarchical memory?Up to 1,872 Kbits of total block RAM?Up to 520 Kbits of total distributed RAMDigital Clock Manager (up to four DCMs)?Clock skew elimination?Frequency synthesis?High resolution phase shifting
Eight global clock lines and abundant routing
Fully supported by Xilinx ISE? and WebPACK? softwaredevelopment systems
MicroBlaze? and PicoBlaze? processor, PCI?,PCIExpress? PIPE Endpoint, and other IP coresPb-free packaging options
Automotive Spartan-3 XA Family variant
?
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Distributed Block
Dedicated
RAM Bits RAM Bits DCMs
Multipliers
(K=1024)(K=1024)
12K30K56K120K208K320K432K520K
72K216K288K432K576K720K1,728K1,872K
4121624324096104
24444444
Maximum
Max.
Differential
User I/O
I/O Pairs124173264391487565633633
5676116175221270300300
Notes:
1.2.Logic Cell = 4-input Look-Up Table (LUT) plus a ‘D’ flip-flop. \otal CLBs\These devices are available in Xilinx Automotive versions as described in DS314: Spartan-3 Automotive XA FPGA Family.DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Introduction and Ordering Information
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Functional Description
The output frequency (fCLKFX) can be expressed as a function of the incoming clock frequency (fCLKIN) as follows:
fCLKFX = fCLKIN(CLKFX_MULTIPLY/CLKFX_DIVIDE)
Equation3
Regarding the two attributes, it is possible to assign any combination of integer values, provided that two conditions are met:??
The two values fall within their corresponding ranges, as specified in Table18.
The fCLKFX frequency calculated from the above expression accords with the DCM’s operating frequencyspecifications.
For example, if CLKFX_MULTIPLY = 5 and CLKFX_DIVIDE = 3, then the frequency of the output clock signal would be 5/3 that of the input clock signal.
DFS Frequency Modes
The DFS supports two operating modes, High Frequency and Low Frequency, with each specified over a different clock frequency range. The DFS_FREQUENCY_MODE attribute chooses between the two modes. When the attribute is set to LOW, the Low Frequency mode permits the two DFS outputs to operate over a low-to-moderate frequency range. When the attribute is set to HIGH, the High Frequency mode allows both these outputs to operate at the highest possible frequencies.
DFS With or Without the DLL
The DFS component can be used with or without the DLL component:
Without the DLL, the DFS component multiplies or divides the CLKIN signal frequency according to the respective CLKFX_MULTIPLY and CLKFX_DIVIDE values, generating a clock with the new target frequency on the CLKFX and CLKFX180 outputs. Though classified as belonging to the DLL component, the CLKIN input is shared with the DFS component. This case does not employ feedback loop; therefore, it cannot correct for clock distribution delay.
With the DLL, the DFS operates as described in the preceding case, only with the additional benefit of eliminating the clock distribution delay. In this case, a feedback loop from the CLK0 output to the CLKFB input must be present.
The DLL and DFS components work together to achieve this phase correction as follows: Given values for the
CLKFX_MULTIPLY and CLKFX_DIVIDE attributes, the DLL selects the delay element for which the output clock edge coincides with the input clock edge whenever mathematically possible. For example, when CLKFX_MULTIPLY = 5 and CLKFX_DIVIDE = 3, the input and output clock edges will coincide every three input periods, which is equivalent in time to five output periods.
Smaller CLKFX_MULTIPLY and CLKFX_DIVIDE values achieve faster lock times. With no factors common to the two attributes, alignment will occur once with every number of cycles equal to the CLKFX_DIVIDE value. Therefore, it is
recommended that the user reduce these values by factoring wherever possible. For example, given CLKFX_MULTIPLY = 9 and CLKFX_DIVIDE = 6, removing a factor of three yields CLKFX_MULTIPLY = 3 and CLKFX_DIVIDE = 2. While both value-pairs will result in the multiplication of clock frequency by 3/2, the latter value-pair will enable the DLL to lock more quickly.
Table 18:DFS Attributes
Attribute
DFS_FREQUENCY_MODECLKFX_MULTIPLYCLKFX_DIVIDE
Frequency multiplier constantFrequency divisor constant
Description
Chooses between High Frequency and Low Frequency modes
Values
Low, High
Integer from 2 to 32Integer from 1 to 32
Table 19:DFS Signals
SignalCLKFXCLKFX180
DirectionOutputOutput
Description
Multiplies the CLKIN frequency by the attribute-value ratio (CLKFX_MULTIPLY/CLKFX_DIVIDE) to generate a clock signal with a new target frequency.
Generates a clock signal with same frequency as CLKFX, only shifted 180° out-of-phase.
DS099 (v3.1) June 27, 2013Product Specification
FPGA可编程逻辑器件芯片XC2S200-5FGG256I中文规格书 - 图文
