Die Level Bank Numbering Overview
Banking and Clocking Summary
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The center clocking backbone contains all vertical clock tracks and clock bufferconnectivity.
The CMT backbone contains all vertical CMT connectivity and is located in the CMTcolumn.
Not all banks are bonded out in every part/package combination.GTP/GTX/GTH columns summary
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One GT Quad=Four transceivers=Four GTPE2 or GTXE2 or GTHE2 primitives.Not all GT Quads are bonded out in every package.
Each bank has four pairs of clock capable (CC) inputs for four differential or foursingle ended clock inputs.----Can connect to the CMT in the same region and the region above and below(with restrictions).
Two MRCC pairs can connect to the BUFRs and BUFIOs in the same region/banksand the regions/banks above and below.
Two SRCC pairs can only connect to the BUFRs and BUFIOs in the same region/bank.
There are no global clock pins (GC pins) in the 7series FPGAs.
?I/O banks summary
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Each user I/O bank has 50 single-ended I/Os or 24 differential pairs (48 differential I/Os). The top and bottom I/O pin are always single ended. All 50 pads of a bank are not always bonded out to pins.
In most devices, banks 14 and 15 always contain the dual-purpose configurationpins. Bank 15 and 35 contains the XADC auxiliary inputs; however, in Kintex-7 devices, the auxiliary inputs are only in bank 15. Bank 0 contains the dedicated configuration pins.
All dedicated configuration I/Os (bank 0) are 3.3V capable.
The multi-function configuration banks 14 and 15 are restricted during
configuration. The SSI technology devices (XC7VX1140T and XC7V2000T) pins in banks 11, 12, 17, 18, 20, and 21 are restricted, similar to multi-function pins. Pins in these banks do not have configuration functions. Because there are architectural differences between these and other banks, special consideration must be taken. For more information, see the State of I/Os During and After Configuration and the
?Bank locations of dedicated and dual-purpose pins
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7 Series FPGAs PackagingUG475 (v1.18) July 16, 2019
Chapter 1:Packaging Overview
XC7K160T and XA7K160T Banks
Figure1-12 shows the I/O and transceiver banks for the XC7K160T and XA7K160T.
FBG484 and FBV484 Package
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HR I/O bank 12 is not bonded out and bank 16 is partially bonded out.HP I/O bank 32 is not bonded out.The GTX Quad 116 is not bonded out.
FBG676, FBV676, FFG676, and FFV676 Packages
All HR and HP I/O banks and the GTX Quads are fully bonded out in these packages.
X-Ref Target - Figure 1-12Left I/OColumn BanksBank 16HRBank 15HRBank 14HRBank 13HRBank 12HRPLL04Right I/OColumnBanksCMTMMCM04PLL03GTX Quad 116QuadGTXCMTMMCM03PLL0216 BUFGs16 BUFGsGTX Quad 115PLL12CMTMMCM02PLL01CMTMMCM12PLL11Bank 34HPBank 33HPBank 32HPHorizontalCenterCMTMMCM01PLL00CMTMMCM11CMTMMCM00HROWPLL10CMTMMCM10Bank50 I/OsCMTBackboneClockingBackboneCMTBackboneUG475_c1_09_122711Figure 1-12:XC7K160T and XA7K160T Banks
7 Series FPGAs PackagingUG475 (v1.18) July 16, 2019
Chapter 1:Packaging Overview
XC7K325T and XQ7K325T Banks
Figure1-13 shows the I/O and transceiver banks for the XC7K325T and XQ7K325T.
FBG676, FBV676, FFG676, FFV676, and RF676 Packages
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HR I/O banks 17 and 18 are not bonded out.All HP I/O banks are fully bonded out.GTX Quads 117 and 118 are not bonded out.
FBG900, FBV900, FFG900, FFV900, and RF900 Packages
All HR and HP I/O banks and the GTX Quads are fully bonded out in these packages.
X-Ref Target - Figure 1-13Left I/OColumn BanksBank 18HRBank 17HRBank 16HRBank 15HRBank 14HRBank 13HRBank 12HRPLL06Right I/OColumnBanksCMTMMCM06PLL05GTX Quad 118QuadGTXCMTMMCM05PLL04GTX Quad 117CMTMMCM04PLL0316 BUFGs16 BUFGsGTX Quad 116HorizontalCenterCMTMMCM03PLL02GTX Quad 115PLL12CMTMMCM02PLL01CMTMMCM12PLL11Bank 34HPBank 33HPBank 32HPBank50 I/OsCMTMMCM01PLL0CMTMMCM11CMTMMCM00HROWPLL10CMTMMCM10CMTBackboneClockingBackboneCMTBackboneUG475_c1_10_081211Figure 1-13:XC7K325T and XQ7K325T Banks
7 Series FPGAs PackagingUG475 (v1.18) July 16, 2019
Chapter 1:Packaging Overview
XC7V585T and XQ7V585T Banks
Figure1-18 shows the I/O and transceiver banks for the XC7V585T and XQ7V585T.
FFG1157 and RF1157 Packages
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All HR I/O banks (11, 12, and 13) are not bonded out.HP I/O banks 31, 32, and 33 are not bonded out.GTX Quads 111, 112, 113, and 119 are not bonded out.
FFG1761 and RF1761 Packages
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X-Ref Target - Figure 1-18HR I/O bank 11 is not bonded out.
All HP I/O banks and the GTX Quads are fully bonded out in these packages.
Left I/OColumn BanksBank 19HPBank 18HPBank 17HPBank 16HPBank 15HPBank 14HPBank 13HRPLL08PLL18Right I/OColumnBanksCMTMMCM08PLL07CMTMMCM18PLL17Bank 39HPBank 38HPBank 37HPBank 36HPBank 35HPBank 34HPBank 33HPBank 32HPBank 31HPGTX Quad 119CMTMMCM07PLL06CMTMMCM17PLL16GTX Quad 118CMTMMCM06PLL05CMTMMCM16PLL15GTX Quad 117CMTMMCM05PLL0416 BUFGs16 BUFGsCMTMMCM15PLL14GTX Quad 116CMTMMCM04PLL03CMTMMCM14PLL13GTX Quad 115CMTMMCM03PLL02CMTMMCM13PLL12GTX Quad 114CMTMMCM02PLL01CMTMMCM12PLL11GTX Quad 113Bank50 I/OsBank 12HRBank 11HRCMTMMCM01PLL00CMTMMCM11GTX Quad 112CMTMMCM00HROWPLL10CMTMMCM10GTX Quad 111Horizontal CenterClockingBackboneCMTBackboneUG475_c1_15_060711Figure 1-18:XC7V585T and XQ7V585T Banks
7 Series FPGAs PackagingUG475 (v1.18) July 16, 2019
Chapter 1:Packaging Overview
7 Series FPGAs PackagingUG475 (v1.18) July 16, 2019
FPGA可编程逻辑器件芯片XCZU15EG-2FFVC900I中文规格书 - 图文
