SIII51001-1.8
Stratix III Device Handbook, Volume 1
Chapter 1:StratixIII Device Family Overview
Features Summary
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Selectable Core Voltage, available in low-voltage devices (L ordering code suffix),enables selection of lowest power or highest performance operation
Up to 16 global clocks, 88 regional clocks, and 116 peripheral clocks per deviceUp to 12 phase-locked loops (PLLs) per device that support PLL reconfiguration,clock switchover, programmable bandwidth, clock synthesis, and dynamic phaseshifting
Memory interface support with dedicated DQS logic on all I/O banks
Support for high-speed external memory interfaces including DDR, DDR2,DDR3SDRAM, RLDRAMII, QDRII, and QDRII+ SRAM on up to 24 modularI/O banks
Up to 1,104 user I/O pins arranged in 24 modular I/O banks that support a widerange of industry I/O standards
Dynamic On-Chip Termination (OCT) with auto calibration support on all I/Obanks
High-speed differential I/O support with serializer/deserializer (SERDES) anddynamic phase alignment (DPA) circuitry for 1.6 Gbps performance
Support for high-speed networking and communications bus standards includingSPI-4.2, SFI-4, SGMII, Utopia IV, 10 Gigabit Ethernet XSBI, Rapid I/O, and NPSIThe only high-density, high-performance FPGA with support for 256-bit AESvolatile and non-volatile security key to protect designsRobust on-chip hot socketing and power sequencing support
Integrated cyclical redundancy check (CRC) for configuration memory errordetection with critical error determination for high availability systems supportBuilt-in error correction coding (ECC) circuitry to detect and correct data errors inM144K TriMatrix memory blocksNios?II embedded processor support
Support for multiple intellectual property megafunctions from Altera? MegaCore?functions and Altera Megafunction Partners Program (AMPPSM)
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Stratix III Device Handbook, Volume 1
Chapter 1:StratixIII Device Family OverviewFeatures Summary
Table1–1 lists the StratixIII FPGA family features.
Table1–1.FPGA Family Features for StratixIII Devices
Device/ FeatureEP3SL50EP3SL70
StratixIII Logic Family
EP3SL110EP3SL150EP3SL200EP3SL340EP3SE50
StratixIII Enhanced Family
EP3SE80EP3SE110EP3SE260
Notes to Table1–1:
(1)MLAB ROM mode supports twice the number of MLAB RAM Kbits.
(2)For total ROM Kbits, use this equation to calculate:
Total ROM Kbits = Total Embedded RAM Kbits + [(# of MLAB blocks × 640)/1024]
(3)The availability of the PLLs shown in this column is based on the device with the largest package. Refer to the Clock Networks and PLLs in Stratix
III Devices chapter in volume 1 of the StratixIII Device Handbook for the availability of the PLLs for each device.
ALMs19K27K43K57K80K135K19K32K43K102K
LEs47.5K67.5K107.5K142.5K200K337.5K47.5K80K107.5K255K
M9K Blocks1081502753554681,040400495639864
Total
M144K MLAB
Embedded
BlocksBlocks
RAM Kbits661216364812121648
9501,3502,1502,8504,0006,7509501,6002,1505,100
1,8362,2144,2035,4999,39616,2725,3286,1838,05514,688
MLAB RAM Kbits (1)2974226728911,2502,1092975006721,594
Total RAM Kbits(2)2,1332,6364,8756,39010,64618,3815,6256,6838,72716,282
18×18-bit Multipliers(FIR Mode)
216288288384576576384672896768
PLLs (3)4488121248812
Stratix III Device Handbook, Volume 1
Chapter 1:StratixIII Device Family Overview
Architecture Features
4×, 6×, 7×, 8×, and 10× SERDES modes when using the dedicated DPA circuitry. DPA minimizes bit errors, simplifies PCB layout and timing management for high-speed data transfer, and eliminates channel-to-channel and channel-to-clock skew in
high-speed data transmission systems. Soft CDR can also be implemented, enabling low-cost 1.6-Gbps clock embedded serial links.
StratixIII devices have the following dedicated circuitry for high-speed differential I/O support:
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Differential I/O bufferTransmitter serializerReceiver deserializerData realignment
Dynamic phase aligner (DPA)Soft CDR functionalitySynchronizer (FIFO buffer)PLLs
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For more information, refer to the High Speed Differential I/O Interfaces with DPA in StratixIII Devices chapter.
Hot Socketing and Power-On Reset
StratixIII devices are hot-socketing compliant. Hot socketing is also known as hot plug-in or hot swap, and power sequencing support without the use of any external devices. Robust on-chip hot-socketing and power-sequencing support ensures proper device operation independent of the power-up sequence. You can insert or remove a StratixIII board in a system during system operation without causing undesirable effects to the running system bus or the board that was inserted into the system. The hot-socketing feature makes it easier to use StratixIII devices on PCBs that also contain a mixture of 3.3-V, 3.0-V, 2.5-V, 1.8-V, 1.5-V, and 1.2-V devices. With the StratixIII hot socketing feature, you do not need to ensure a specific power-up sequence for each device on the board.
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For more information, refer to the Hot Socketing and Power-On Reset in StratixIII Devices chapter.
Configuration
StratixIII devices are configured using one of the following four configuration schemes:
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Fast passive parallel (FPP)Fast active serial (AS)Passive serial (PS)
Joint Test Action Group (JTAG)
All configuration schemes use either an external controller (for example, a MAX?II device or microprocessor), a configuration device, or a download cable.
Stratix III Device Handbook, Volume 1
Chapter 1:StratixIII Device Family OverviewArchitecture Features
StratixIII devices support configuration data decompression, which saves
configuration memory space and time. This feature allows you to store compressed configuration data in configuration devices or other memory and transmit this compressed bitstream to StratixIII devices. During configuration, the StratixIII device decompresses the bitstream in real time and programs its SRAM cells.StratixIII devices support decompression in the FPP when using a MAXII device/microprocessor plus flash, fast AS, and PS configuration schemes. The
StratixIII decompression feature is not available in the FPP when using the enhanced configuration device and JTAG configuration schemes.
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For more information, refer to the Configuring StratixIII Devices chapter.
Stratix III Device Handbook, Volume 1
Chapter 1:StratixIII Device Family Overview
Architecture Features
The design security feature is available when configuring StratixIII FPGAs using the fast passive parallel (FPP) configuration mode with an external host (such as a MAXII device or microprocessor), or when using fast active serial (AS) or passive serial (PS) configuration schemes.
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For more information about the design security feature, refer to the Design Security in StratixIII Devices chapter.
SEU Mitigation
StratixIII devices have built-in error detection circuitry to detect data corruption due to soft errors in the configuration random-access memory (CRAM) cells. This feature allows all CRAM contents to be read and verified continuously during user mode operation to match a configuration-computed CRC value. The enhanced CRC circuit and frame-based configuration architecture allows detection and location of multiple, single, and adjacent bit errors which, in conjunction with a soft circuit supplied as a reference design, allows don’t-care soft errors in the CRAM to be ignored during device operation. This provides a steep decrease in the effective soft error rate, increasing system reliability.
On-chip memory block SEU mitigation is also offered using the ninth bit and a configurable megafunction in the QuartusII software for MLAB and M9K blocks while the M144K memory blocks have built-in error correction code (ECC) circuitry.
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For more information about the dedicated error detection circuitry, refer to the SEU Mitigation in StratixIII Devices chapter.
Programmable Power
StratixIII delivers Programmable Power, the only FPGA with user programmable power options balancing today’s power and performance requirements. StratixIII devices utilize the most advanced power-saving techniques, including a variety of process, circuit, and architecture optimizations and innovations. In addition, user controllable power reduction techniques provide an optimal balance of performance and power reduction specific for each design configured into the StratixIII FPGA. The QuartusII software (starting from version 6.1) automatically optimizes designs to meet the performance goals while simultaneously leveraging the programmable power-saving options available in the StratixIII FPGA without the need for any changes to the design flow.
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For more information about Programmable Power in StratixIII devices, refer to the following documents:
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Programmable Power and Temperature Sensing Diode in StratixIII Devices chapterAN 437: Power Optimization in StratixIII FPGAsStratixIII Programmable Power White Paper
Stratix III Device Handbook, Volume 1
FPGA可编程逻辑器件芯片EP3SE260F1152C2N中文规格书 - 图文
