Power Consumption
Power
Consumption
Altera? offers two ways to calculate power for a design: the Excel-based PowerPlay Early Power Estimator power calculator and the Quartus?II PowerPlay Power Analyzer feature.
The interactive Excel-based PowerPlay Early Power Estimator is typically used prior to designing the FPGA in order to get an estimate of device power. The QuartusII PowerPlay Power Analyzer provides better quality estimates based on the specifics of the design after place-and-route is complete. The Power Analyzer can apply a combination of user-entered, simulation-derived and estimated signal activities which, combined with detailed circuit models, can yield very accurate power estimates.
In both cases, these calculations should only be used as an estimation of power, not as a specification.
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For more information about PowerPlay tools, refer to the PowerPlay Early Power Estimator User Guide and the PowerPlay Early Power Estimator and PowerPlay Power Analyzer chapters in volume 3 of the QuartusII Handbook.
The PowerPlay Early Power Estimator is available on the Altera web site at www.altera.com. See Table5–4 on page5–3 for typical ICC standby specifications.
Timing Model
The DirectDriveTM technology and MultiTrackTM interconnect ensure predictable performance, accurate simulation, and accurate timing analysis across all StratixII device densities and speed grades. This
section describes and specifies the performance, internal timing, external timing, and PLL, high-speed I/O, external memory interface, and JTAG timing specifications.
All specifications are representative of worst-case supply voltage and junction temperature conditions.1
The timing numbers listed in the tables of this section are extracted from the QuartusII software version 5.0 SP1.
Preliminary & Final Timing
Timing models can have either preliminary or final status. The QuartusII software issues an informational message during the design compilation if the timing models are preliminary. Table5–33 shows the status of the StratixII device timing models.
Stratix II Device Handbook, Volume 1
Timing Model
Figure5–3.Input Register Setup & Hold Timing Diagram
Input Data Delaymicro tSUmicro tHInput Clock DelayFor output timing, different I/O standards require different baseline loading techniques for reporting timing delays. Altera characterizes timing delays with the required termination for each I/O standard and with 0 pF (except for PCI and PCI-X which use 10 pF) loading and the timing is specified up to the output pin of the FPGA device. The
QuartusII software calculates the I/O timing for each I/O standard with a default baseline loading as specified by the I/O standards.
The following measurements are made during device characterization. Altera measures clock-to-output delays (tCO) at worst-case process,
minimum voltage, and maximum temperature (PVT) for default loading conditions shown in Table5–34. Use the following equations to calculate clock pin to output pin timing for StratixII devices.
tCO from clock pin to I/O pin = delay from clock pad to I/O output register + IOE output register clock-to-output delay + delay from output register to output pin + I/O output delay
txz/tzx from clock pin to I/O pin = delay from clock pad to I/O output register + IOE output register clock-to-output delay + delay from output register to output pin + I/O output delay + output enable pin delay
Simulation using IBIS models is required to determine the delays on the PCB traces in addition to the output pin delay timing reported by the QuartusII software and the timing model in the device handbook.1.
Simulate the output driver of choice into the generalized test setup,using values from Table5–34.Record the time to VMEAS.
Simulate the output driver of choice into the actual PCB trace andload, using the appropriate IBIS model or capacitance value torepresent the load.
2.3.
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
However, when the output is a double data rate input/output (DDIO) signal, both edges of the input clock signal (positive and negative) trigger output transitions (Figure5–9). Therefore, any distortion on the input clock and the input clock buffer affect the output DCD.
Figure5–9.DCD Measurement Technique for DDIO (Double-Data Rate) Outputs
IOEVCCINPUTVCCDFFPRNDQclkCLRNinst2OUTPUToutputDFFPRNGNDNOTDQinst8CLRNinst3When an FPGA PLL generates the internal clock, the PLL output clocks the IOE block. As the PLL only monitors the positive edge of the reference clock input and internally re-creates the output clock signal, any DCD present on the reference clock is filtered out. Therefore, the DCD for a DDIO output with PLL in the clock path is better than the DCD for a DDIO output without PLL in the clock path.
Tables5–80 through 5–87 give the maximum DCD in absolution
derivation for different I/O standards on StratixII devices. Examples are also provided that show how to calculate DCD as a percentage.Table5–80.Maximum DCD for Non-DDIO Output on Row I/O Pins(Part 1 of2)Note(1)Row I/O Output
Standard
3.3-V LVTTTL3.3-V LVCMOS2.5 V
Maximum DCD for Non-DDIO Output-3 Devices
245125105
-4 & -5 Devices
275155135
Unit
pspsps
Stratix II Device Handbook, Volume 1
FPGA可编程逻辑器件芯片EP3CLS70U484C7中文规格书
