Feature Descriptions
SGMII GTX Transceiver Clock Generation
[Figure1-2, callout 16]
An Integrated Circuit Systems ICS844021I chip (U2) generates a high-quality, low-jitter, 125MHz LVDS clock from a 25MHz crystal (X3). This clock is sent to FPGA U1, Bank 113 GTX
transceiver (clock pins AH8 (P) and AH7 (N)) driving the SGMII interface. Series AC coupling capacitors are present to allow the clock input of the FPGA to set the common mode voltage. Figure1-17 shows the Ethernet SGMII clock source.
X-Ref Target - Figure 1-17C30018pF 50VNPOVDDA_SGMIICLKVDD_SGMIICLKU2X325.00 MHz1X11SGMIICLK_XTAL_OUT3ICS844021I-01Clock GeneratorOEVDDAXTAL_OUTVDDQ0587SGMIICLK_Q0_C_PR3201.0MΩ 5?0118pF 50VNPO2GND2C280.1μF 25VX5RSGMIICLK_Q0_P4GND2X23SGMIICLK_XTAL_IN42XTAL_INGNDNQ06SGMIICLK_Q0_C_NSGMIICLK_Q0_NC290.1μF 25VX5RUG885_c1_17_020612GND_SGMIICLKGND_SGMIICLKGND_SGMIICLKFigure 1-17:Ethernet 125 MHz SGMII GTX Clock
References
Details about the tri-mode Ethernet MAC core are provided in LogiCORE IP Tri-Mode Ethernet MAC Product Guide for Vivado Design Suite (PG051) [Ref9] and in the LogiCORE IP Tri-Mode Ethernet MAC v4.5 User Guide (UG138) [Ref13].
The product brief for the Marvell 88E1111 Alaska Gigabit Ethernet Transceiver can be found at the Marvell website [Ref21].
The data sheet can be obtained under NDA with Marvell. Contact information is at the Marvell website [Ref21].
For more information about the ICS844021 device, go to the Integrated Device Technology website [Ref22] and search for part number ICS844021.
USB-to-UART Bridge
[Figure1-2, callout 17]
The VC707 board contains a Silicon Labs CP2103GM USB-to-UART bridge device (U44) which allows a connection to a host computer with a USB port. The USB cable is supplied in the VC707 Evaluation Kit (Type-A end to host computer, Type mini-B end to VC707 board connector J17). The CP2103GM is powered by the USB 5V provided by the host PC when the USB cable is plugged into the USB port on the VC707 board.
Xilinx UART IP is expected to be implemented in the FPGA logic. The FPGA supports the
USB-to-UART bridge using four signal pins: Transmit (TX), Receive (RX), Request to Send (RTS), and Clear to Send (CTS).
Silicon Labs provides royalty-free Virtual COM Port (VCP) drivers for the host computer. These drivers permit the CP2103GM USB-to-UART bridge to appear as a COM port to communications application software (for example, TeraTerm) that runs on the host computer. The VCP device
VC707 Evaluation Board
UG885 (v1.8) February 20, 2019
Chapter 1:VC707 Evaluation Board Features
VC707 Evaluation BoardUG885 (v1.8) February 20, 2019
Feature Descriptions
Table 1-28:J37 VITA 57.1 FMC 2 HPC Connections (Cont’d)
I/O U1 FPGA StandardPin
LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18
U39T39AD40AD41AJ42AK42AD42AE42Y39AA39AJ40AJ41V33V34W32W33R33R34W36W37V39V40T36R37
J37
FMC 2
Schematic Net Name
HPC Pin
G2G3G6G7G9G10G12G13G15G16G18G19G21G22G24G25G27G28G30G31G33G34G36G37G39
FMC2_HPC_CLK1_M2C_PFMC2_HPC_CLK1_M2C_NFMC2_HPC_LA00_CC_PFMC2_HPC_LA00_CC_NFMC2_HPC_LA03_PFMC2_HPC_LA03_NFMC2_HPC_LA08_PFMC2_HPC_LA08_NFMC2_HPC_LA12_PFMC2_HPC_LA12_NFMC2_HPC_LA16_PFMC2_HPC_LA16_NFMC2_HPC_LA20_PFMC2_HPC_LA20_NFMC2_HPC_LA22_PFMC2_HPC_LA22_NFMC2_HPC_LA25_PFMC2_HPC_LA25_NFMC2_HPC_LA29_PFMC2_HPC_LA29_NFMC2_HPC_LA31_PFMC2_HPC_LA31_NFMC2_HPC_LA33_PFMC2_HPC_LA33_NVADJ
J37 FMC 2 HPC Pin
H1H2H4H5H7H8H10H11H13H14H16H17H19H20H22H23H25H26H28H29H31H32H34H35H37H38H40
Schematic Net Name
I/O U1 FPGA StandardPin
NC
FMC2_HPC_PRSNT_M2C_BFMC2_HPC_CLK0_M2C_PFMC2_HPC_CLK0_M2C_NFMC2_HPC_LA02_PFMC2_HPC_LA02_NFMC2_HPC_LA04_PFMC2_HPC_LA04_NFMC2_HPC_LA07_PFMC2_HPC_LA07_NFMC2_HPC_LA11_PFMC2_HPC_LA11_NFMC2_HPC_LA15_PFMC2_HPC_LA15_NFMC2_HPC_LA19_PFMC2_HPC_LA19_NFMC2_HPC_LA21_PFMC2_HPC_LA21_NFMC2_HPC_LA24_PFMC2_HPC_LA24_NFMC2_HPC_LA28_PFMC2_HPC_LA28_NFMC2_HPC_LA30_PFMC2_HPC_LA30_NFMC2_HPC_LA32_PFMC2_HPC_LA32_NVADJ
LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18
AG32AF39AF40AK39AL39AL41AL42AC40AC41Y42AA42AC38AC39U32U33P35P36U34T35V35V36T32R32P37P38
VC707 Evaluation Board
UG885 (v1.8) February 20, 2019
Chapter 1:VC707 Evaluation Board Features
Table 1-28:J37 VITA 57.1 FMC 2 HPC Connections (Cont’d)
I/O U1 FPGA StandardPin
J37
FMC 2 HPC Pin
K1K4
LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18
AA29AA30AC31AD31AE34AE35AF35AF36AB36AB37Y35AA36AM16AN16BB19BB18AM18AM17AL19AM19AJ18AJ17
K5K7K8K10K11K13K14K16K17K19K20K22K23K25K26K28K29K31K32K34K35K37K38
J37 FMC 2
Schematic Net Name
HPC Pin
J2J3J6J7J9J10J12J13J15J16J18J19J21J22J24J25J27J28J30J31J33J34J36J37
NCNC
FMC2_HPC_HA03_PFMC2_HPC_HA03_NFMC2_HPC_HA07_PFMC2_HPC_HA07_NFMC2_HPC_HA11_PFMC2_HPC_HA11_NFMC2_HPC_HA14_PFMC2_HPC_HA14_NFMC2_HPC_HA18_PFMC2_HPC_HA18_NFMC2_HPC_HA22_PFMC2_HPC_HA22_NFMC2_HPC_HB01_PFMC2_HPC_HB01_NFMC2_HPC_HB07_PFMC2_HPC_HB07_NFMC2_HPC_HB11_PFMC2_HPC_HB11_NFMC2_HPC_HB15_PFMC2_HPC_HB15_NFMC2_HPC_HB18_PFMC2_HPC_HB18_N
Schematic Net Name
I/O U1 FPGA StandardPin
NCNCNC
FMC2_HPC_HA02_PFMC2_HPC_HA02_NFMC2_HPC_HA06_PFMC2_HPC_HA06_NFMC2_HPC_HA10_PFMC2_HPC_HA10_NFMC2_HPC_HA17_CC_PFMC2_HPC_HA17_CC_NFMC2_HPC_HA21_PFMC2_HPC_HA21_NFMC2_HPC_HA23_PFMC2_HPC_HA23_NFMC2_HPC_HB00_CC_PFMC2_HPC_HB00_CC_NFMC2_HPC_HB06_CC_PFMC2_HPC_HB06_CC_NFMC2_HPC_HB10_P FMC2_HPC_HB10_N FMC2_HPC_HB14_P FMC2_HPC_HB14_N FMC2_HPC_HB17_CC_PFMC2_HPC_HB17_CC_NFMC2_VIO_B_M2C
LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18
AC30AD30AB31AB32AF31AF32AC34AD35AA34AA35Y37AA37AT17AU17AY18AY17AP20AR19AK19AK18AW18AW17BANK 32
VCCO
J39FMC2_VIO_B_M2C
BANK 32 VCCO
K40
Notes:
1.No I/O standards are associated with MGT connections.
VC707 Evaluation BoardUG885 (v1.8) February 20, 2019
Chapter 1:VC707 Evaluation Board Features
VC707 Evaluation BoardUG885 (v1.8) February 20, 2019
FPGA可编程逻辑器件芯片XC2S150-4FG456I中文规格书 - 图文
