2.Intel Agilex I/O Features and UsageUG-20214 | 2021.04.05
?????
If the data bus size value is SIZE, the LSB is at the right-most position.If the data bus size value is 2 × SIZE, the bus is made of two words of SIZE .If the data bus size value 4 × SIZE, the bus is made of four words of SIZE.The LSB is in the right-most position of each word.
The right-most word specifies the first word going out for output buses and thefirst word coming in for input buses.
Related InformationInput Path on page 37
Data Interface Signals and Corresponding ClocksTable 18.
Data Interface Signals and Corresponding Clocks
Parameter Configuration
Register Mode
Half Rate Logic
Off
Separate input/output Clocks
Off
Clock Signal Name
Signal Name
din??SimpleRegisterDDIO
ck
DDIO??
SimpleRegisterDDIO
OnOff
OffOn
ck_hrck_in
DDIO
??
OnOff
OnOff
ck_hr_inck
doutoe
??SimpleRegisterDDIO
DDIO??
SimpleRegisterDDIO
OnOff
OffOn
ck_hrck_out
DDIO
???
OnOff
OnOff
ck_hr_outck
sclrsset
All pad signals
??SimpleRegisterDDIO
DDIO??
SimpleRegisterDDIO
OnOff
OffOn
ck_fr
??
Input path: ck_inOutput path: ck_outInput path: ck_fr_inOutput path: ck_fr_out
DDIOOnOn??
Guideline: Swap datain_h and datain_l Ports in Migrated IP
When you migrate your GPIO IP from previous devices to the GPIO IP, you can turn onUse legacy top-level port names option in the GPIO IP parameter editor. However,the behavior of these ports in the GPIO IP is different than in the IP used for theStratix V, Arria V, and Cyclone V devices.
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2.Intel Agilex I/O Features and Usage
UG-20214 | 2021.04.05
The GPIO IP drives these ports to the output registers on these clock edges:??
datain_h—on the falling edge of outclockdatain_l—on the rising edge of outclock
If you migrated your GPIO IP from Stratix V, Arria V, and Cyclone V devices, swap thedatain_h and datain_l ports when you instantiate the IP generated by the GPIO IP.Related Information
GPIO Intel FPGA IP Parameter Settings on page 27
2.3.2.3. GPIO Intel FPGA IP Architecture
The GPIO IP supports the GPIO components and features of Intel Agilex device family.You can use the Intel Quartus Prime parameter editor to configure the GPIO IP.Components of the GPIO IP:???
Double data rate input/output (DDIO)—halves or doubles the data-rate of acommunication channel
Delay chains—configure the delay chains to perform specific delay and assist inI/O timing closure
I/O buffers—connect the pads to the FPGA
2.3.2.3.1. GPIO Intel FPGA IP Data PathsFigure 18.
High-Level View of Single-Ended GPIO
CoreOEIN[1:0]DATAIN[3:0]DATAOUT[3:0]
GPIOOEPathOutputPathInputPathBufferTable 19.
Data PathGPIO IP Data Path Modes
Register ModeBypassSimple RegisterFull-RateDDR I/OHalf-RateThe full-rate DDIOoperates as a regularDDIO. The half-rateDDIOs convert full-ratedata to half-rate data.InputData goes from thedelay element to thecore, bypassing alldouble data rate I/Os(DDIOs).The full-rate DDIOoperates as a simpleregister, bypassing half-rate DDIOs. The Fitterchooses whether to packthe register in the I/O orimplement the registerThe full-rate DDIOoperates as a regularDDIO, bypassing thehalf-rate DDIOs.continued... Send Feedback
2.Intel Agilex I/O Features and UsageUG-20214 | 2021.04.05
Data Path
Bypass
Register Mode
Simple Register
Full-Rate
in the core, dependingon the area and timingtrade-offs.
DDR I/O
Half-Rate
Output
Data goes from the corestraight to the delayelement, bypassing allDDIOs.
The full-rate DDIOoperates as a simpleregister, bypassing half-rate DDIOs. The Fitterchooses whether to packthe register in the I/O orimplement the registerin the core, dependingon the area and timingtrade-offs.
The full-rate DDIOoperates as a simpleregister. The outputbuffer drives both anoutput pin and an inputbuffer.
The full-rate DDIOoperates as a regularDDIO, bypassing thehalf-rate DDIOs.
The full-rate DDIOoperates as a regularDDIO. The half-rateDDIOs convert full-ratedata to half-rate data.
Bidirectional
The output buffer drivesboth an output pin andan input buffer.
The full-rate DDIOoperates as a regularDDIO. The output bufferdrives both an outputpin and an input buffer.The input buffer drives aset of three flip-flops.
The full-rate DDIOoperates as a regularDDIO. The half-rateDDIOs convert full-ratedata to half-rate. Theoutput buffer drives bothan output pin and aninput buffer. The inputbuffer drives a set ofthree flip-flops.
If you use asynchronous clear and preset signals, all DDIOs share these same signals.Half-rate and full-rate DDIOs connect to separate clocks. When you use half-rate andfull-rate DDIOs, the full-rate clock must run at twice the half-rate frequency. You canuse different phase relationships to meet timing requirements.
Input Path
The pad sends data to the input buffer, and the input buffer feeds the delay element.After the data goes to the output of the delay element, the programmable bypassmultiplexers select the features and paths to use.
Each input path contains two stages of DDIOs, which are full-rate and half-rate.
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FPGA可编程逻辑器件芯片EP3C10U256C8N中文规格书
