St_4 St_5 St_6
IF OP= Read or Write or Jmp or Jz St_4 MAR?PC THEN IR（7..0）?M_data_in Write-Read?’0’ IF OP= （Read）THEN St_5 Write-Read?’0’ MAR?IR(11..0) IF OP= （Write） THEN MAR?IR(11..0) MDR?(R0) IF OP= （Jmp） THEN PC?IR(11..0) MAR?IR(11..0) IF OP= （Jz） IF (R0)= 0 THEN PC?IR(11..0) MAR?IR(11..0) ELSE MAR?(PC) IF OP= （Jmp） THEN PC?IR(11..0) MAR?IR(11..0) IF OP= （Jz） IF (R0)= 0 THEN PC?IR(11..0) MAR?IR(11..0) ELSE MAR?(PC) IF OP= （Jmp）or OP= （Jz） St_0 MAR?(PC) Write-Read?’0’ IF OP=（Read） St_6 MAR?(PC) Write-Read?’0’ IF OP=（Write） St_6 MAR?(PC) Write-Read?’1’ IF OP=（Read）THEN St_0 Write-Read?’0’ R0?M_data_in 六．六、
CPU的Verilog HDL代码：
module cpu(reset, clock, Write_Read, M_address, M_data_in, M_data_out, overflow); input reset; input clock;
output Write_Read; output [11:0] M_address;
6 <0>
input [7:0] M_data_in; output [7:0] M_data_out; output overflow; reg overflow;
reg [15:0] IR; reg [7:0] MDR; reg [11:0] MAR; reg [2:0] status; parameter idle =4'b0000, load =4'b0001, move =4'b0010, addp =4'b0011, subp =4'b0100, mulp =4'b0101, logp =4'b0110, comp =4'b0111, sh =4'b1000, meth1 =4'b1001, swap =4'b1010, jmp =4'b1011, jz =4'b1100, read =4'b1101, write =4'b1110, stop =4'b1111;
always @(negedge reset or posedge clock ) begin: status_change if (reset == 1'b0) status <= 0; else
case (status) 0 :
status <= 1; 1 :
if (IR[15:12] == stop) status <= 1; else
status <= 2; 2 :
7 <0>
case (IR[15:12])
swap, jmp, jz, read, write : status <= 3; default :
status <= 0; endcase 3 :
if (IR[15:12] == swap) status <= 0; else
status <= 4; 4 :
status <= 5; 5 :
case (IR[15:12]) read :
status <= 6; default :
status <= 0; endcase default :
status <= 0; endcase // end
always @(negedge reset or negedge clock) begin: seq
reg [11:0] PC; reg [7:0] R0; reg [7:0] R1; reg [7:0] R2; reg [7:0] R3; reg [7:0] A; reg [8:0] temp; reg [15:0] temp2; if (reset == 1'b0) begin
IR <= {16{1'b0}}; PC = {12{1'b0}}; R0 = {8{1'b0}}; R1 = {8{1'b0}}; R2 = {8{1'b0}};
8 <0>
R3 = {8{1'b0}}; A = {8{1'b0}};
MAR <= {12{1'b0}}; MDR <= {8{1'b0}}; end else begin
overflow <= 1'b0; case (status) 0 :
begin
IR <= {M_data_in, 8'b00000000}; PC = PC + 1'b1; end 1 :
begin
if (IR[15:12] != stop) MAR <= PC; case (IR[15:12]) load :
R0 = {4'b0000, IR[11:8]}; move :
case (IR[11:8]) 4'b0001 : R0 = R1; 4'b0010 : R0 = R2; 4'b0011 : R0 = R3; 4'b0100 : R1 = R0; 4'b0110 : R1 = R2; 4'b0111 : R1 = R3; 4'b1000 : R2 = R0; 4'b1001 : R2 = R1; 4'b1011 : R2 = R3; 4'b1100 : R3 = R0; 4'b1101 :
9 <0>
R3 = R1; 4'b1110 : R3 = R2; default : ; endcase sh :
case (IR[11:10]) 2'b00 :
case (IR[9:8]) 2'b00 :
R0 = {R0[7], R0[7:1]}; 2'b01 :
R1 = {R1[7], R1[7:1]}; 2'b10 :
R2 = {R2[7], R2[7:1]}; default :
R3 = {R3[7], R3[7:1]}; endcase 2'b01 :
case (IR[9:8]) 2'b00 :
R0 = {R0[6:0], R0[0]}; 2'b01 :
R1 = {R0[6:0], R1[0]}; 2'b10 :
R2 = {R0[6:0], R2[0]}; default :
R3 = {R0[6:0], R3[0]}; endcase 2'b10 :
case (IR[9:8]) 2'b00 :
R0 = {1'b0, R0[7:1]}; 2'b01 :
R1 = {1'b0, R1[7:1]}; 2'b10 :
R2 = {1'b0, R2[7:1]}; default :
R3 = {1'b0, R3[7:1]}; endcase default :
case (IR[9:8]) 2'b00 :
10 <0>
CPU课程设计
