TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001 12-Bit-Resolution A/D Converter 10-?s Conversion Time Over Operating Temperature 11 Analog Input Channels 3 Built-In Self-Test Modes Inherent Sample-and-Hold Function Linearity Error . . . ? 1 LSB Max On-Chip System Clock End-of-Conversion Output Unipolar or Bipolar Output Operation (Signed Binary With Respect to 1/2 the Applied Voltage Reference) Programmable MSB or LSB First Programmable Power Down
Programmable Output Data Length CMOS Technology
Application Report Available?
DB, DW, J, OR N PACKAGE (TOP VIEW) AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC EOC I/O CLOCK DATA INPUT DATA OUT CS REF + REF – AIN10 AIN9 FN PACKAGE (TOP VIEW)
description
The TLC2543C and TLC2543I are 12-bit, switched- capacitor, successive-approximation, analog-to- digital converters. Each device, with three control inputs [chip select (CS), the input-output clock, and the address input (DATA INPUT)], is designed for communication with the serial port of a host processor or peripheral through a serial 3-state output. The device allows high-speed data transfers from the host.
AIN3 AIN4 AIN5 AIN6 AIN7
3 2 1 20 19 4 18
17 5 6 7 8
9 10 11 12 13
16 15 14
AIN2 AIN1 AIN0 VCC EOC I/O CLOCK DATA INPUT DATA OUT CS REF +
AIN8 GND AIN9 AIN10 REF– Copyright ? 2001, Texas Instruments Incorporated In addition to the high-speed converter and versatile control capability, the device has an on-chip 14-channel
multiplexer that can select any one of 11 inputs or any one of three internal self-test voltages. The sample-and-hold function is automatic. At the end of conversion, the end-of-conversion (EOC) output goes high to indicate that conversion is complete. The converter incorporated in the device features differential high-impedance reference inputs that facilitate ratiometric conversion, scaling, and isolation of analog circuitry from logic and supply noise. A switched-capacitor design allows low-error conversion over the full operating temperature range.
The TLC2543C is characterized for operation from TA = 0?C to 70?C. The TLC2543I is characterized for operation from TA = – 40?C to 85?C. The TLC2543M is characterized for operation from TA = – 55?C to 125?C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
? Microcontroller Based Data Acquisition Using the TLC2543 12-bit Serial-Out ADC (SLAA012)
PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.
?
On products compliant to MIL-PRF-38535, all parameters are testedunless otherwise noted. On all other products, productionprocessing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 752651
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001
AVAILABLE OPTIONS
TA 0?C to 70?C –40?C to 85?C –55?C to 125?C ? Available in tape and reel and ordered as the TLC2543CDBLE, TLC2543IDBR, TLC2543CDWR, TLC2543IDWR, TLC2543CFNR, or
TLC2543IFNR.
SMALL OUTLINE ? ? (DB) (DW) TLC2543CDB TLC2543CDW TLC2543IDB TLC2543IDW — — PACKAGE PLASTIC CHIP CARRIER (FN) ? TLC2543CFN TLC2543IFN — CERAMIC DIP (J) — — TLC2543MJ PLASTIC DIP (N) TLC2543CN TLC2543IN —
functional block diagram
REF + 14
AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10
1 2 3 4 5 6 7 8 9 11 12
REF – 13
14-Channel Analog Multiplexer
4
Sample-and- Hold Function
Input Address Register
12-Bit Analog-to-Digital Converter (Switched Capacitors)
12
Output 12 Data Register
12-to-1 Data Selector and Driver 4
16
DATA OUT
3
Self-Test Reference
Control Logic and I/O Counters
DATA INPUT I/O CLOCK
CS
17 18 15
19 EOC
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 ?
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001
Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. AIN0 – AIN10 1–9, I Analog input. These 11 analog-signal inputs are internally multiplexed. The driving source impedance should 11, 12 be less than or equal to 50 ? for 4.1-MHz I/O CLOCK operation and be capable of slewing the analog input voltage into a capacitance of 60 pF. CS 15 I Chip select. A high-to-low transition on CS resets the internal counters and controls and enables DATA OUT, DATA INPUT, and I/O CLOCK. A low-to-high transition disables DATA INPUT and I/O CLOCK within a setup time. DATA INPUT 17 I Serial-data input. A 4-bit serial address selects the desired analog input or test voltage to be converted next. The serial data is presented with the MSB first and is shifted in on the first four rising edges of I/O CLOCK. are read into the address register, I/O CLOCK clocks the remaining bits in order. After the four address bits for the A/D conversion result. DATA OUT is in the high-impedance state when CS DATA OUT 16 O The 3-state serial output CS is low. With a valid CS, DATA OUT is removed from the high-impedance state is high and active when? of the previous conversion result. The level corresponding to the MSB/LSB valueand is driven to the logicnext falling edge of I/O CLOCK drives DATA OUT to the logic level corresponding to the next MSB / LSB, and the remaining bits are shifted out in order. EOC 19 O End of conversion. EOC goes from a high to a low logic level after the falling edge of the last I/O CLOCK and remains low until the conversion is complete and the data is ready for transfer. GND 10 Ground. GND is the ground return terminal for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND. I/O CLOCK 18 I Input/output clock. I/O CLOCK receives the serial input and performs the following four functions: 1. It clocks the eight input data bits into the input data register on the first eight rising edges of I/O CLOCK with the multiplexer address available after the fourth rising edge. 2. On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplexer input capacitor array and continues to do so until the last falling edge of the I/O begins charging theCLOCK. 3. It shifts the 11 remaining bits of the previous conversion data out on DATA OUT. Data changes on the falling edge of I/O CLOCK. 4. It transfers control of the conversion to the internal state controller on the falling edge of the last I/O CLOCK. REF + 14 I Positive reference voltage The upper reference voltage value (nominally is appliedVCC) to REF+. The maximum input voltage range is determined by the difference between the voltage applied to this terminal and REF – terminal. the voltage applied to the The lower reference voltage value (nominally ground) is applied to REF –. REF – 13 I Negative reference voltage. Positive supply voltage VCC ? VCC MSB/LSB = Most significant bit / least significant bit
POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265
3
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001
absolute noted)?
maximum ratings over operating free-air temperature range (unless otherwise
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6.5 V Input voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC + 0.3 V Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC + 0.3 V Positive reference voltage, Vref + . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.1 V Negative reference voltage, Vref – . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.1 V Peak input current, II (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? 20 mA Peak total input current, II (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? 30 mA Operating free-air temperature range, TA: TLC2543C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0?C to 70?C
TLC2543I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40?C to 85?C TLC2543M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55?C to 125?C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65?C to 150?C Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260?C
? Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the GND terminal with REF – and GND wired together (unless otherwise noted).
recommended operating conditions MIN NOM MAX UNIT Supply voltage, VCC 4.5 5 5.5 V (seeV VCC Vref + Note 2) Positive reference voltage, (see0 V Negative reference voltage, Vref – Note 2) – 2.5 +0.1V Differential reference voltage, Vref +Vref (see– Note 2) VCC VCC Analog input voltage (see Note 2) 0 V VCC High-level control input voltage, 2 V VCC VIH Low-level control input voltage, VCC0.8 V VCC VIL Clock frequency at I/O CLOCK VCC 0 4.1 MHz 100 ns Setup time, address bits at DATA INPUT before I/O CLOCK?, tsu(A) (see Figure 4) 0 ns Hold time, address bits after I/O CLOCK?, th(A) (see Figure 4) 0 ns Hold time, CS low after last I/O CLOCK?, th(CS) (see Figure 5) (see1.425 ?s Setup time, CS low before clocking in first address bit, tsu(CS) Note 3 and Figure 5) Pulse duration, I/O CLOCK high, twH(I/O) 120 ns Pulse duration, I/O CLOCK low, 120 ns twL(I/O) Transition time, I/O CLOCK high to low, (see Note 4 and Figure 6) 1 ?s tt(I/O) Transition time, DATA INPUT and CS, tt(CS) 10 ?s TLC2543C 0 70 Operating free-air temperature, ?C TLC2543I –40 85 TA TLC2543M –55 125 NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (111111111111), while input voltages less than that applied
to REF– convert as all zeros (000000000000).
3. To minimize errors caused by noise at the CS input, the internal circuitry waits for a setup time after CS? before responding to control input signals. No attempt should be made to clock in an address until the minimum CS setup time has elapsed.
4. This is the time required for the clock input signal to fall from VIHmin to VILmax or to rise from VILmax to VIHmin. In the vicinity of normal room temperature, the devices function with input clock transition time as slow as 1 ?s for remote data acquisition applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor. 4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 ?
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001
electrical characteristics over recommended operating free-air temperature range, VCC = Vref+ = 4.5 V to 5.5 V, f(I/O CLOCK) = 4.1 MHz (unless otherwise noted) TLC2543C, TLC2543I PARAMETER TEST CONDITIONS ? MAX MIN TYP = 4.5 V, 2.4 VCC IOH = –1.6 mA VOH VCC = 4.5 V to 5.5 V, IOH = –20 ?A VCC VOH VCC = 4.5 V, 0.4 VOL VCC IOL = 1.6 mA 0.1 VCC = 4.5 V to 5.5 V, IOL = 20 ?A VOL = CS atVCC 1 2.5 High-impedanceg off-sVO VCC, = 0, CS atVCC 1 –2.5 tate output VO IOZ= 1 2.5 IIH current VI VCC IIH 1 –2.5 IIL VI IIL VI at 0 V CS1 2.5 ICC ICC For all digital inputs, 4 25 ICC(PD) 0 ? VI ? 0.5 V or VI ? VCC – 0.5 V ICC(PD) Selected channel at 1 VCC, Unselected channel at 0 V Selected channel leakage Selected channel at 0 V, current –1 Unselected channel at VCC Maximum static analog = = GND 1 2.5 Vref + VCC, Vref – reference current into REF + Analog inputs 30 60 C Input Control inputs 5 15 i capacitance ? All typical values are at VCC = 5 V, TA = 25?C.
electrical characteristics over recommended operating free-air temperature range, VCC = Vref+ = 4.5 V to 5.5 V, f(I/O CLOCK) = 4.1 MHz (unless otherwise noted) TLC2543M PARAMETER TEST CONDITIONS ? MAX MIN TYP = 4.5 V, 2.4 VCC IOH = –1.6 mA VOH VCC = 4.5 V to 5.5 V, IOH = –20 ?A VCC VOH VCC = 4.5 V, 0.4 VOL VCC IOL = 1.6 mA 0.1 VCC = 4.5 V to 5.5 V, IOL = 20 ?A VOL = CS atVCC 1 2.5 High-impedanceg off-sVO VCC, = 0, CS atVCC 1 –2.5 tate output VO IOZ= 1 10 IIH current VI VCC IIH 1 –10 IIL VI IIL VI at 0 V CS1 2.5 ICCICC For all digital inputs, 4 25 ICC(PD) 0 ? VI ? 0.5 V or VI ? VCC – 0.5 V ICC(PD) Selected channel at 10 VCC, Unselected channel at 0 V Selected channel leakage Selected channel at 0 V, current –10 Unselected channel at VCC Maximum static analog = = GND 1 2.5 Vref + VCC, Vref – reference current into REF + Analog inputs 30 60 C Input Control inputs 5 15 i capacitance ? All typical values are at VCC = 5 V, TA = 25?C.
POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265
UNIT V V ?A ?A ?A mA ?A ?A ?A pF UNIT V V ?A ?A ?A mA ?A ?A ?A pF
5
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001
operating characteristics over recommended operating free-air temperature range, VCC = Vref+ = 4.5 V to 5.5 V, f(I/O CLOCK) = 4.1 MHz ? PARAMETER TEST CONDITIONS UNIT MIN TYP MAX See Figure 2 LSB ?1 EL EL See Figure 2 LSB ?1 ED ED See Note 2 and LSB ?1.5 EO Figure 2 EO See Note 2 and LSB ?1 EG Figure 2 EGLSB ?1.75 ET ET DATA INPUT = 1011 2048 Self-test output code (see Table 3 and Note 8) DATA INPUT = 1100 0 DATA INPUT = 1101 4095 See Figures 9 –14 8 10 ?s t(conv) 10 + total t(conv) See Figures 9 –14 I/O CLOCK ?s tc and Note 9 periods + tc td(I/O-EOC) I/O See Figures 9 –14 tacq 4 12 CLOCK and Note 9 tacq periods See Figure 6 10 ns tv Valid time, DATA OUT remains valid after I/O CLOCK? See Figure 6 150 ns td(I/O-DATA) Delay time, I/O CLOCK? to DATA OUT valid See Figure 7 1.5 2.2 ?s td(I/O-EOC) Delay time, last I/O CLOCK? to EOC? See Figure 8 100 ns td(EOC-DATA) Delay time, EOC? to DATA OUT (MSB / LSB) See Figure 3 0.7 1.3 ?s tPZH, tPZL Enable time, CS? to DATA OUT (MSB / LSB driven) tPHZ, tPLZ Disable time, CS? to DATA OUT (high impedance) See Figure 3 70 150 ns tr(EOC) See Figure 8 15 50 ns tr(EOC) See Figure 7 15 50 ns tf(EOC) tf(EOC) See Figure 6 15 50 ns tr(bus) tr(bus) See Figure 6 15 50 ns tf(bus) tf(bus) Delay time, last I/O CLOCK? to CS? to abort conversion td(I/O-CS)5 ?s (see Note 10) ? All typical values are at TA = 25?C.
NOTES: 2. Analog input voltages greater than that applied to REF + convert as all ones (111111111111), while input voltages less than that
applied to REF – convert as all zeros (000000000000).
5. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
6. Gain error is the difference between the actual midstep value and the nominal midstep value in the transfer diagram at the specified gain point after the offset error has been adjusted to zero. Offset error is the difference between the actual midstep value and the nominal midstep value at the offset point.
7. Total unadjusted error comprises linearity, zero-scale, and full-scale errors. 8. Both the input address and the output codes are expressed in positive logic. 9. I/O CLOCK period = 1 /(I/O CLOCK frequency) (see Figure 7).
10. Any transitions of CS are recognized as valid only when the level is maintained for a setup time. CS must be taken low at ? 5 ?s
of the tenth I/O CLOCK falling edge to ensure a conversion is aborted. Between 5 ?s and 10 ?s, the result is uncertain as to whether the conversion is aborted or the conversion results are valid. 6 POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001
PARAMETER MEASUREMENT INFORMATION
15 V 50 ?
C1 C2 0.1 ?F 470 pF VI C1 10 ?F C2 0.1 ?F _ U1 + 10 ? TLC2543
AIN0–AIN10 C3 470 pF 50 ?
LOCATION U1 C1 C2 C3 DESCRIPTION
Figure 1. Analog Input Buffer to Analog Inputs AIN0 – AIN10
Test Point OP27 10-?F 35-V tantalum capacitor 0.1-?F ceramic NPO SMD capacitor 470-pF porcelain Hi-Q SMD capacitor VCC
RL = 2.18 k?
–15 V PART NUMBER — — AVX 12105C104KA105 or equivalent Johanson 201S420471JG4L or equivalent
Test Point VCC RL = 2.18 k?
DATA OUT
EOC
CL = 50 pF 12 k?
CL = 100 pF 12 k?
Figure 2. Load Circuits
2V
0.8 V
Data Valid CS
tPZH, tPZL
tPHZ, tPLZ 90% 10%
DATA INPUT
tsu(A) 2V 0.8 V th(A)
DATA OUT
2.4 V 0.4 V I/O CLOCK
0.8 V Figure 3. DATA OUT to Hi-Z Voltage Waveforms
Figure 4. DATA INPUT and I/O CLOCK
Voltage Waveforms
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 ?
7
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001
PARAMETER MEASUREMENT INFORMATION
CS
tsu(CS) I/O CLOCK
0.8 V Last Clock 0.8 V 2V th(CS) 0.8 V NOTE A: To ensure full conversion accuracy, it is recommended that no input signal change occurs while a conversion is ongoing.
Figure 5. CS and I/O CLOCK Voltage Waveforms
tt(I/O)
tt(I/O) 2V 0.8 V
I/O CLOCK Period
td(I/O-DATA)
tv
DATA OUT
0.8 V
I/O CLOCK
2V 0.8 V
2.4 V 0.4 V 2.4 V 0.4 V
tr(bus), tf(bus)
Figure 6. I/O CLOCK and DATA OUT Voltage Waveforms
I/O CLOCK
Last Clock td(I/O-EOC) 0.8 V EOC 2.4 V 0.4 V
tf(EOC) Figure 7. I/O CLOCK and EOC Voltage Waveforms
tr(EOC) EOC
0.4 V 2.4 V
DATA OUT
2.4 V 0.4 V td(EOC-DATA)
Valid MSB Figure 8. EOC and DATA OUT Voltage Waveforms
8
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 ?
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001
CS
(see Note A)
PARAMETER MEASUREMENT INFORMATION
1
I/O CLOCK
2 3 4 5 6 7 8 11 12 1
Access Cycle B
Sample Cycle B
DATA OUT
A11 A10 A9 A8 A7 A6 A5 A4 A1 A0
Previous Conversion Data
LSB
Hi-Z State
B11
MSB
DATA INPUT
MSB
EOC
B7 B6 B5 B4
LSB
B3 B2 B1 B0 C7
Shift in New Multiplexer Address, Simultaneously Shift Out Previous
Conversion Value
t(conv) A/D Conversion Interval
Initialize Initialize
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS? before responding to control input signals.
Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 9. Timing for 12-Clock Transfer Using CS With MSB First
CS
(see Note A)
1
I/O CLOCK
2 3 4 5 6 7 8 11 12 1
Access Cycle B
Sample Cycle B
DATA OUT
A11
B11
A10 A9 A8 A7 A6 A5 A4 A1 A0 Low Level
Previous Conversion Data
MSB
DATA INPUT
LSB
MSB
EOC
B7 B6 B5 B4
LSB
B3 B2 B1 B0 C7
Shift in New Multiplexer Address, Simultaneously Shift Out Previous
Conversion Value
Initialize
t(conv)
A/D Conversion
Interval Initialize
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS? before responding to control input signals.
Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 10. Timing for 12-Clock Transfer Not Using CS With MSB First
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 ?
9
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001
PARAMETER MEASUREMENT INFORMATION
CS (see Note A)
I/O CLOCK
1 2 3 4 5 6 7 8 1
Access Cycle B
Sample Cycle B
Hi-Z
DATA OUT
A7
B7
A6 A5 A4 A3 A2 A1 A0
Previous Conversion Data
LSB
MSB
DATA INPUT
EOC
B7MSB
B6 B5 B4
LSB
B3 B2 B1 B0
C7
Shift in New Multiplexer Address, Simultaneously Shift Out Previous
Conversion Value
Initialize
t(conv) A/D Conversion Interval
Initialize
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS? before responding to control input signals.
Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 11. Timing for 8-Clock Transfer Using CS With MSB First
CS
(see Note A)
I/O CLOCK
1 2 3 4 5 6 7 8 1 Access Cycle B Sample Cycle B
B7
DATA OUT
A7 A6 A5 A4 A3 A2 A1 A0 Low Level
Previous Conversion Data
LSB
MSB
DATA INPUT
B7MSB
EOC
B6 B5 B4
LSB
B3 B2 B1 B0
C7
Initialize
Shift in New Multiplexer Address, Simultaneously Shift Out Previous
Conversion Value
t(conv) A/D Conversion Interval
Initialize
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS? before responding to control input signals.
Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 12. Timing for 8-Clock Transfer Not Using CS With MSB First
10
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 ?
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001
PARAMETER MEASUREMENT INFORMATION
CS
(see Note A)
I/O CLOCK
1 2 3 4 5 6 7 8 15 16 1
Access Cycle B Sample Cycle B
DATA OUT
A15 A14 A13 A12 A11 A10 A9 A8 A1 A0
Previous Conversion Data
LSB
Hi-Z State
B15
MSB
DATA INPUT
MSB
EOC
B7 B6 B5 B4
LSB
B3 B2 B1 B0
C7
Shift in New Multiplexer Address, Simultaneously Shift Out Previous
Conversion Value
Initialize
t(conv) A/D Conversion
Interval
Initialize
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS? before responding to control input signals.
Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 13. Timing for 16-Clock Transfer Using CS With MSB First
CS
(see Note A)
I/O CLOCK
1 2 3 4 5 6 7 8 15 16 1
Access Cycle B
Sample Cycle B
DATA OUT
A15 A14 A13 A12 A11 A10 A9 A8 A1 A0
Previous Conversion Data
LSB
Low Level
B15
MSB
DATA INPUT
EOC
MSB
B7 B6 B5 B4
LSB
B3 B2 B1 B0
C7
Initialize
Shift in New Multiplexer Address, Simultaneously Shift Out Previous
Conversion Value
t(conv) A/D Conversion Interval
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS? before responding to control input signals.
Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 14. Timing for 16-Clock Transfer Not Using CS With MSB First
POST OFFICE BOX 655303 DALLAS, TEXA?S 75265
11
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001
Initially, with chip select (CS) high, I/O CLOCK and DATA INPUT are disabled and DATA OUT is in the high-impedance state. CS going low begins the conversion sequence by enabling I/O CLOCK and DATA INPUT and removes DATA OUT from the high-impedance state.
The input data is an 8-bit data stream consisting of a 4-bit analog channel address (D7 – D4), a 2-bit data length select (D3 – D2), an output MSB or LSB first bit (D1), and a unipolar or bipolar output select bit (D0) that are applied to DATA INPUT. The I/O CLOCK sequence applied to the I/O CLOCK terminal transfers this data to the input data register.
During this transfer, the I/O CLOCK sequence also shifts the previous conversion result from the output data register to DATA OUT. I/O CLOCK receives the input sequence of 8, 12, or 16 clock cycles long depending on the data-length selection in the input data register. Sampling of the analog input begins on the fourth falling edge of the input I/O CLOCK sequence and is held after the last falling edge of the I/O CLOCK sequence. The last falling edge of the I/O CLOCK sequence also takes EOC low and begins the conversion. converter operation
The operation of the converter is organized as a succession of two distinct cycles: 1) the I/O cycle and 2) the actual conversion cycle. I/O cycle
The I/O cycle is defined by the externally provided I/O CLOCK and lasts 8, 12, or 16 clock periods, depending on the selected output data length.
During the I/O cycle, the following two operations take place simultaneously.
An 8-bit data stream consisting of address and control information is provided to DATA INPUT. This data is shifted into the device on the rising edge of the first eight I/O CLOCKs. DATA INPUT is ignored after the first eight clocks during 12- or 16-clock I/O transfers.
The data output, with a length of 8, 12, or 16 bits, is provided serially on DATA OUT. When CS is held low, the first output data bit occurs on the rising edge of EOC. When CS is negated between conversions, the first output data bit occurs on the falling edge of CS. This data is the result of the previous conversion period, and after the first output data bit, each succeeding bit is clocked out on the falling edge of each succeeding I/O CLOCK. conversion cycle
The conversion cycle is transparent to the user, and it is controlled by an internal clock synchronized to I/O CLOCK. During the conversion period, the device performs a successive-approximation conversion on the analog input voltage. The EOC output goes low at the start of the conversion cycle and goes high when conversion is complete and the output data register is latched. A conversion cycle is started only after the I/O cycle is completed, which minimizes the influence of external digital noise on the accuracy of the conversion.
PRINCIPLES OF OPERATION
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265 ?
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001
power up and initialization
PRINCIPLES OF OPERATION
After power up, CS must be taken from high to low to begin an I/O cycle. EOC is initially high, and the input data register is set to all zeroes. The contents of the output data register are random, and the first conversion result should be ignored. To initialize during operation, CS is taken high and is then returned low to begin the next I/O cycle. The first conversion after the device has returned from the power-down state may not read accurately due to internal device settling.
Table 1. Operational Terminology
Current (N) I/O cycle Current (N) conversion cycle The entire I/O CLOCK sequence that transfers address and control data into the data register and clocks from the previous conversion from DATA OUT the digital resultThe conversion cycle starts immediately after the current I/O cycle. The end of the current I/O cycle is the edge in the I/O CLOCK sequence. The current conversion result is loaded into the output last clock falling conversion is complete. register when Current (N) conversion result Previous (N –1) conversion cycle Next (N + 1) I/O cycle The current conversion result is serially shifted out on the next I/O cycle. The I/O period that follows the current conversion cycle The conversion cycle just prior to the current I/O cycle Example: In the 12-bit mode, the result of the current conversion cycle is a 12-bit serial-data stream clocked out during
the next I/O cycle. The current I/O cycle must be exactly 12 bits long to maintain synchronization, even
when this corrupts the output data from the previous conversion. The current conversion is begun immediately after the twelfth falling edge of the current I/O cycle.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
?
13
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001
data input
PRINCIPLES OF OPERATION
The data input is internally connected to an 8-bit serial-input address and control register. The register defines the operation of the converter and the output data length. The host provides the data word with the MSB first. Each data bit is clocked in on the rising edge of the I/O CLOCK sequence (see Table 2 for the data input-register format).
Table 2. Input-Register Format
INPUT DATA BYTE
FUNCTION SELECT
L1 L0 LSBF BIP ADDRESS BITS D7
(MSB) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
D6 D5 D4 D3 D2 D1 D0
(LSB)
Select input channel
AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 Select test voltage
(Vref + – Vref –)/2 Vref – Vref +
Software power down Output data length
8 bits 12 bits 16 bits Output data format
MSB first
LSB first (LSBF) Unipolar (binary) Bipolar (BIP) 2s complement ? X represents a do not care condition.
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
0 X? 1
1 0 1
0 1
0 1
data input address bits
The four MSBs (D7 – D4) of the data register address one of the 11 input channels, a reference-test voltage, or the power-down mode. The address bits affect the current conversion, which is the conversion that immediately follows the current I/O cycle. The reference voltage is nominally equal to Vref+ – Vref –.
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TLC2543芯片手册 - 时序 - 转换原理
