FPGA可编程逻辑器件芯片XC2V1000-5FGG456I中文规格书

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Chapter 2: XPHY Architecture

Clocking

Each XPIO bank has two XPLLs. Each XPLL has four user-controlled clock outputs

(XPLL.CLKOUT<0-3>) to the programmable logic (PL) and a dedicated, high-speed clock

connection (XPLL.CLKOUTPHY) to all XPHY nibbles in an XPIO bank. For more information onXPLLs, see the Versal ACAP Clocking Resources Architecture Manual (AM003). The following tablessummarize XPHY clocking ports and attributes. For more complete descriptions, see Ports and Attributes.

Table 3: XPHY Clocks

Clock

PLL_CLKCTRL_CLKFIFO_RD_CLK

CLK_FROM_OTHER_XPHYNCLK_NIBBLE_INPCLK_NIBBLE_INFIFO_WR_CLKCLK_TO_LOWER

I/O

InputInputInputInputInputInputOutputOutput

Description

Clocks the XPHY interfaceRIU/delay line/BISC clockThe FIFO read clockInter-byte clock inputN-clk input for inter-nibbleclocking

P-clk input for inter-nibbleclocking

The FIFO write clock. Generatedinternally.

Inter-byte clock output to certainnumerically lower nibbles (withone exception to a numericallyhigher nibble).

Inter-byte clock output to certainnumerically higher nibbles.N-clk output for inter-nibbleclocking

P-clk output for inter-nibbleclocking

Strobes/capture clocks can bereceived through the IOB to

NIBBLESLICE[0] or through inter-nibble/inter-byte clocking. Withinthe XPHY the strobe is separatedinto a p-clk and n-clk, which thencan be used for inter-nibbleclocking and data capture.

For source-synchronous receiveinterfaces (implying SERIAL_MODE= FALSE), the strobe/capture clockis received with the data with aknown phase relationship. Forother receive interfaces (implyingSERIAL_MODE = TRUE), the

capture clock is generated withinthe XPHY from PLL_CLK. Inter-nibble and inter-byte clockingaren't supported whenSERIAL_MODE = TRUE

CLK_TO_UPPERNCLK_NIBBLE_OUTPCLK_NIBBLE_OUTStrobe/Capture clock

OutputOutputOutputInput (RX)Output (TX)

AM010 (v1.2) April 2, 2021

Versal ACAP SelectIO Resources Architecture Manual

Chapter 2: XPHY Architecture

Table 4: Clocking Connections

Clock

PLL_CLKCTRL_CLKFIFO_RD_CLK

CLK_FROM_OTHER_XPHY

InputInputInputInput

I/OConnection (TX)

XPLL.CLKOUTPHY

Does not need to come from aspecific clock source

––

Connection (RX)

XPLL.CLKOUTPHY

Does not need to come from aspecific clock source.

Depends on FIFO_MODE_x. Refer to Controlling FIFO Modes.

If receiving an inter-byte clock,connect to the applicable

CLK_TO_LOWER or CLK_TO_UPPER ofthe source nibble sending the inter-byte clock.

If receiving inter-nibble clocks,connect PCLK_NIBBLE_OUT of thesource nibble to PCLK_NIBBLE_IN ofthe destination nibble. Do the samefor NCLK_NIBBLE_OUT andNCLK_NIBBLE_IN.

Generated internally from thestrobe or in the case of

SERIAL_MODE = TRUE, fromPLL_CLK.

If sending an inter-byte clock,connect the applicable

CLK_TO_LOWER or CLK_TO_UPPER ofthe source nibble to

CLK_FROM_OTHER_XPHY of thedestination nibble receiving theinter-byte clock.

If sending inter-nibble clocks,connect PCLK_NIBBLE_OUT of thesource nibble to PCLK_NIBBLE_IN ofthe destination nibble. Do the samefor NCLK_NIBBLE_OUT andNCLK_NIBBLE_IN.

For source-synchronous interfaces,a strobe/capture clock must bereceived by NIBBLESLICE[0]

(DATAIN[0]), inter-nibble clocking(see Table 3 for the ports), or inter-byte clocking (see Table 3 for theports). If a strobe/capture clock isreceived on NIBBLESLICE[0],

regardless of whether it is single-ended or differential,

DELAY_VALUE_0 (and only

DELAY_VALUE_0) must be set to 0. Ifa source-synchronous interfacespans multiple nibbles, inter-nibbleand/or inter-byte clocking can beused to forward the strobe.

If SERIAL_MODE = TRUE, the captureclock is generated from the PLL_CLKinput for each nibble in the

interface. Inter-nibble and inter-byte clocking are not supportedwhen SERIAL_MODE = TRUE.

PCLK_NIBBLE_IN,NCLK_NIBBLE_IN

Input–

FIFO_WR_CLKOutput–

CLK_TO_LOWER,CLK_TO_UPPER

Output–

PCLK_NIBBLE_OUT,NCLK_NIBBLE_OUT

Output–

Strobe/Capture clock

Output or input,depending onwhich

perspective- RX(input) or TX(output).