FPGA可编程逻辑器件芯片XC2S300E-5FTG256C中文规格书 - 图文

Spartan-3 FPGA Family: DC and Switching Characteristics

Digital Clock Manager (DCM) Timing

For specification purposes, the DCM consists of three key components: the Delay-Locked Loop (DLL), the Digital Frequency Synthesizer (DFS), and the Phase Shifter (PS).

Aspects of DLL operation play a role in all DCM applications. All such applications inevitably use the CLKIN and the CLKFB inputs connected to either the CLK0 or the CLK2X feedback, respectively. Thus, specifications in the DLL tables (Table58 and Table59) apply to any application that only employs the DLL component. When the DFS and/or the PS components are used together with the DLL, then the specifications listed in the DFS and PS tables (Table60 through Table63) supersede any corresponding ones in the DLL tables. DLL specifications that do not change with the addition of DFS or PS functions are presented in Table58 and Table59.

Period jitter and cycle-cycle jitter are two (of many) different ways of characterizing clock jitter. Both specifications describe statistical variation from a mean value.

Period jitter is the worst-case deviation from the average clock period of all clock cycles in the collection of clock periods sampled (usually from 100,000 to more than a million samples for specification purposes). In a histogram of period jitter, the mean value is the clock period.

Cycle-cycle jitter is the worst-case difference in clock period between adjacent clock cycles in the collection of clock periods sampled. In a histogram of cycle-cycle jitter, the mean value is zero.

Delay-Locked Loop (DLL)

Table 58:Recommended Operating Conditions for the DLL

Speed Grade

Symbol

Input Frequency RangesFCLKIN

CLKIN_FREQ_DLL_LFCLKIN_FREQ_DLL_HF

Input Pulse RequirementsCLKIN_PULSE

CLKIN pulse width as a

percentage of the CLKIN period

FCLKIN ≤ 100 MHzFCLKIN > 100 MHz

LowHighAllAll

40E%––––

Allowable variation of off-chip feedback delay from the DCM output to the CLKFB input

–

60U%

40E%–––––

60U%

--pspsnsns

Frequency for the CLKIN input

LowHigh

18(2)48

167(3)280(3)

18(2)48

167(3)280(3)(4)

MHzMHz

Description

Frequency Mode/FCLKIN Range

Min

-5Max

Min

-4Max

Units

Input Clock Jitter Tolerance and Delay Path Variation(5)CLKIN_CYC_JITT_DLL_LFCLKIN_CYC_JITT_DLL_HFCLKIN_PER_JITT_DLL_LF CLKIN_PER_JITT_DLL_HF CLKFB_DELAY_VAR_EXT

Cycle-to-cycle jitter at the CLKIN input

Period jitter at the CLKIN input

±300±150±1±1

±300±150±1±1

Notes:

1.DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.

2.3.4.5.

The DFS, when operating independently of the DLL, supports lower FCLKIN frequencies. See Table60.

The CLKIN_DIVIDE_BY_2 attribute can be used to increase the effective input frequency range up to FBUFG. When set to TRUE,CLKIN_DIVIDE_BY_2 divides the incoming clock frequency by two as it enters the DCM.

Industrial temperature range devices have additional requirements for continuous clocking, as specified in Table64.CLKIN input jitter beyond these limits may cause the DCM to lose lock. See UG331 for more details.

DS099 (v3.1) June 27, 2013Product Specification

Spartan-3 FPGA Family: DC and Switching Characteristics

DS099 (v3.1) June 27, 2013Product Specification

Spartan-3 FPGA Family: DC and Switching Characteristics

DS099 (v3.1) June 27, 2013Product Specification

Spartan-3 FPGA Family: Pinout Descriptions

Table 72:Dual-Purpose Configuration Pins for Parallel (SelectMAP) Configuration Modes (Cont’d)

Pin NameBUSY

DirectionOutput

Description

Configuration Data Rate Control for Parallel Mode:

In the Slave and Master Parallel modes, BUSY throttles the rate at which configuration data is loaded. BUSY is only necessary if CCLK operates at greater than 50 MHz. Ignore BUSY for frequencies of 50 MHz and below.

When BUSY is Low, the FPGA accepts the next configuration data byte on the next rising CCLK edge for which CS_B and RDWR_B are Low. When BUSY is High, the FPGA ignores the next configuration data byte. The next configuration data value must be held or reloaded until the next rising CCLK edge when BUSY is Low. When CS_B is High, BUSY is in a high impedance state.

BUSY01Hi-Z

Function

The FPGA is ready to accept the next configuration data byte.

The FPGA is busy processing the current configuration data byte and is not ready to accept the next byte.

If CS_B is High, then BUSY is high impedance.

This signal is located in Bank 4 and its output voltage is determined by VCCO_4. The BitGen option Persist permits this pin to retain its configuration function in the User mode.

INIT_B

Bidirectional (open-drain)

Initializing Configuration Memory/Configuration Error (active-Low):See description under Serial Configuration Modes, page112.

JTAG Configuration ModeIn the JTAG configuration mode all dual-purpose configuration pins are unused and behave exactly like user-I/O pins, as shown in Table79. See Table75 for Mode Select pin settings required for JTAG mode.

Dual-Purpose Pin I/O Standard During ConfigurationDuring configuration, the dual-purpose pins default to CMOS input and output levels for the associated VCCO voltage supply pins. For example, in the Parallel configuration modes, both VCCO_4 and VCCO_5 are required. If connected to +2.5V, then the associated pins conform to the LVCMOS25 I/O standard. If connected to +3.3V, then the pins drive LVCMOSoutput levels and accept either LVTTL or LVCMOS input levels.

Dual-Purpose Pin Behavior After ConfigurationAfter the configuration process completes, these pins, if they were borrowed during configuration, become user-I/O pins available to the application. If a dual-purpose configuration pin is not used during the configuration process—i.e., the parallel configuration pins when using serial mode—then the pin behaves exactly like a general-purpose I/O. See I/O Type: Unrestricted, General-purpose I/O Pins section.

DCI: User I/O or Digitally Controlled Impedance Resistor Reference Input

These pins are individual user-I/O pins unless one of the I/O standards used in the bank requires the Digitally Controlled Impedance (DCI) feature. If DCI is used, then 1% precision resistors connected to the VRP_# and VRN_# pins match the impedance on the input or output buffers of the I/O standards that use DCI within the bank. The ‘#’ character in the pin name indicates the associated I/O bank and is an integer, 0 through 7.

There are two DCI pins per I/O bank, except in the CP132 and TQ144 packages, which do not have any DCI inputs forBank 5.

VRP and VRN Impedance Resistor Reference Inputs

The 1% precision impedance-matching resistor attached to the VRP_# pin controls the pull-up impedance of PMOS transistor in the input or output buffer. Consequently, the VRP_# pin must connect to ground. The ‘P’ character in “VRP” indicates that this pin controls the I/O buffer’s PMOS transistor impedance. The VRP_# pin is used for both single and split termination.

DS099 (v3.1) June 27, 2013Product Specification

Spartan-3 FPGA Family: Pinout Descriptions

The 1% precision impedance-matching resistor attached to the VRN_# pin controls the pull-down impedance of NMOS transistor in the input or output buffer. Consequently, the VRN_# pin must connect to VCCO. The ‘N’ character in “VRN” indicates that this pin controls the I/O buffer’s NMOS transistor impedance. The VRN_# pin is only used for split termination.Each VRN or VRP reference input requires its own resistor. A single resistor cannot be shared between VRN or VRP pins associated with different banks.

During configuration, these pins behave exactly like user-I/O pins. The associated DCI behavior is not active or valid until after configuration completes.

Also see Digitally Controlled Impedance (DCI), page16.

DCI Termination Types

If the I/O in an I/O bank do not use the DCI feature, then no external resistors are required and both the VRP_# and VRN_# pins are available for user I/O, as shown in section [a] of Figure42.

If the I/O standards within the associated I/O bank require single termination—such as GTL_DCI, GTLP_DCI, or

HSTL_III_DCI—then only the VRP_# signal connects to a 1% precision impedance-matching resistor, as shown in section [b]of Figure42. A resistor is not required for the VRN_# pin.

Finally, if the I/O standards with the associated I/O bank require split termination—such as HSTL_I_DCI, SSTL2_I_DCI, SSTL2_II_DCI, or LVDS_25_DCI and LVDSEXT_25_DCI receivers—then both the VRP_# and VRN_# pins connect to separate 1% precision impedance-matching resistors, as shown in section [c] of Figure42. Neither pin is available for user I/O.

X-Ref Target - Figure 42One of eightI/O BanksOne of eightI/O BanksOne of eightI/O BanksVCCORREF (1%)User I/OUser I/OVRNVRPRREF (1%)VRNVRPRREF (1%)(a)No termination(b)Single termination(c)Split terminationDS099-4_03_091910Figure 42:DCI Termination Types

GCLK: Global Clock Buffer Inputs or General-Purpose I/O Pins

These pins are user-I/O pins unless they specifically connect to one of the eight low-skew global clock buffers on the device, specified using the IBUFG primitive.

There are eight GCLK pins per device and two each appear in the top-edge banks, Bank 0 and 1, and the bottom-edge banks, Banks 4 and 5. See Figure40 for a picture of bank labeling.During configuration, these pins behave exactly like user-I/O pins.Also see Global Clock Network, page42.

CONFIG: Dedicated Configuration Pins

The dedicated configuration pins control the configuration process and are not available as user-I/O pins. Every package has seven dedicated configuration pins. All CONFIG-type pins are powered by the +2.5V VCCAUX supply.Also see Configuration, page46.

DS099 (v3.1) June 27, 2013Product Specification