半导体传感器ADG1402BRMZ-REEL7中文规格书 - 图文

Data Sheet

ADG633

SPECIFICATIONS

DUAL-SUPPLY OPERATION

VDD = +5 V, VSS = ?5 V, GND = 0 V, TA = ?40°C to +125°C, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ΔRON On-Resistance Flatness, RFLAT(ON) LEAKAGE CURRENTS Source Off Leakage, IS(OFF) Drain Off Leakage, ID(OFF) Channel On Leakage, ID(ON), IS(ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS1 tTRANSITION tON (EN) tOFF (EN) Break-Before-Make Time Delay, tBBM Charge Injection Off Isolation Total Harmonic Distortion, THD + N Channel-to-Channel Crosstalk ?3 dB Bandwidth CS(OFF) CD(OFF) CD(ON), CS(ON) POWER REQUIREMENTS2 IDD ISS 12

+25°C 52 75 0.8 1.3 9 12 ±0.005 ±0.2 ±0.005 ±0.2 ±0.005 ±0.2 0.005 2 60 90 70 95 25 40 40 2 4 ?90 0.025 ?90 580 4 7 12 0.01 0.01 ?40°C to +85°C 90 1.8 13 110 120 45 ?40°C to +125°C VSS to VDD 100 2 14 ±5 ±5 ±5 2.4 0.8 ±1 130 135 50 10 1 1 Unit V Ω typ Ω max Ω typ Ω max Ω typ Ω max nA typ nA max nA typ nA max nA typ nA max V min V max μA typ μA max pF typ ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ pC max dB typ % typ dB typ MHz typ pF typ pF typ pF typ μA typ μA max μA typ μA max Test Conditions/Comments VDD = +4.5 V, VSS = ?4.5 V VS = ±4.5 V, IS = 1 mA; see Figure 20 VS = ±4.5 V, IS = 1 mA; see Figure 20 VS = +3.5 V, IS = 1 mA VS = +3.5 V, IS = 1 mA VDD = +5 V, VSS = ?5 V, VS = ±3 V, IS = 1 mA VDD = +5 V, VSS = ?5 V, VS = ±3 V, IS = 1 mA VDD = +5.5 V, VSS = ?5.5 V VD = ±4.5 V, VS = +4.5 V; see Figure 21 VD = ±4.5 V, VS = +4.5 V; see Figure 21 VD = ±4.5 V, VS = + 4.5 V; see Figure 22 VD = ±4.5 V, VS = + 4.5 V; see Figure 22 VD = VS = ±4.5 V; see Figure 23 VD = VS = ±4.5 V; see Figure 23 VIN = VINL or VINH VIN = VINL or VINH RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 24 RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 24 RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 26 RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 26 RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 26 RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 26 RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3 V; see Figure 25 RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3 V; see Figure 25 VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 27 VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 27 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28 RL = 600 Ω, 2 V p-p, f = 20 Hz to 20 kHz RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 30 RL = 50 Ω, CL = 5 pF; see Figure 29 f = 1 MHz f = 1 MHz f = 1 MHz VDD = +5.5 V, VSS = ?5.5 V Digital inputs = 0 V or 5.5 V Digital inputs = 0 V or 5.5 V Digital inputs = 0 V or 5.5 V Digital inputs = 0 V or 5.5 V Guaranteed by design; not subject to production test.

The device is fully specified at a ±5 V dual supply and at 5 V and 3.3 V single supplies. It is possible to operate the ADG633 with unbalanced supplies or at other voltage supplies ( ±2 V to ±6 V, and 2 V to 12 V); however, the switch characteristics change. These changes include, but are not limited to: analog signal range, on resistance, leakage, VINL, VINH, and switching times. The optimal power-up sequence for the device is: ground, VDD, VSS, and then the digital inputs, before applying the analog input signal.

Rev. B | Page 3 of 16

ADG633

SINGLE-SUPPLY OPERATION

VDD = 5 V, VSS = 0 V, GND = 0 V, TA = ?40°C to +125°C, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ΔRON On-Resistance Flatness, RFLAT(ON) LEAKAGE CURRENTS Source Off Leakage, IS(OFF) Drain Off Leakage, ID(OFF) Channel On Leakage, ID(ON), IS(ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS1 tTRANSITION tON (EN) tOFF (EN) Break-Before-Make Time Delay, tBBM Charge Injection Off Isolation Channel-to-Channel Crosstalk ?3 dB Bandwidth CS(OFF) CD(OFF) CD(ON), CS(ON) POWER REQUIREMENTS2 IDD 12

Data Sheet

+25°C ?40°C to +85°C ?40°C to +125°C 0 to VDD Unit V Ω typ Ω max Ω typ Ω max Ω typ nA typ nA max nA typ nA max nA typ nA max V min V max μA typ μA max pF typ ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ pC max dB typ dB typ MHz typ pF typ pF typ pF typ μA typ μA max Test Conditions/Comments VDD = 4.5 V, VSS = 0 V VS = 0 V to 4.5 V, IS = 1 mA; see Figure 20 VS = 0 V to 4.5 V, IS = 1 mA; see Figure 20 VS = +3.5 V, IS = 1 mA VS = +3.5 V, IS = 1 mA VDD = 5 V, VSS = 0 V, VS = 1.5 V to 4 V, IS = 1 mA VDD = 5.5 V VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 21 VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 21 VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 22 VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 22 VS = VD = 1 V or 4.5 V; see Figure 23 VS = VD = 1 V or 4.5 V; see Figure 23 85 150 4.5 8 13 ±0.005 ±0.2 ±0.005 ±0.2 ±0.005 ±0.2 160 200 9 14 10 16 ±5 ±5 ±5 2.4 0.8 0.005 ±1 2 100 150 100 150 25 35 90 0.5 1 ?90 ?90 520 5 8 12 0.01 1 VIN = VINL or VINH VIN = VINL or VINH 190 190 45 220 220 50 10 RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 24 RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 24 RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 26 RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 26 RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 26 RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 26 RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3 V; see Figure 25 RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3 V; see Figure 25 VS = 2.5 V, RS = 0 Ω, CL = 1 nF; see Figure 27 VS = 2.5 V, RS = 0 Ω, CL = 1 nF; see Figure 27 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 30 RL = 50 Ω, CL = 5 pF; see Figure 29 f = 1 MHz f = 1 MHz f = 1 MHz VDD = 5.5 V Digital inputs = 0 V or 5.5 V Digital inputs = 0 V or 5.5 V Guaranteed by design; not subject to production test.

The device is fully specified at a ±5 V dual supply and at 5 V and 3.3 V single supplies. It is possible to operate the ADG633 with unbalanced supplies or at other voltage supplies ( ±2 V to ±6 V, and 2 V to 12 V); however, the switch characteristics change. These changes include, but are not limited to: analog signal range, on resistance, leakage, VINL, VINH, and switching times. The optimal power-up sequence for the device is: ground, VDD, VSS, and then the digital inputs, before applying the analog input signal.

Rev. B | Page 4 of 16