SIII52001-2.3
Electrical Characteristics
This chapter describes the electrical characteristics, switching characteristics, and I/O timing for Stratix?III devices. Electrical characteristics include operating conditions and power consumption. Switching characteristics include core performance specifications and periphery performance. A glossary is also included for your reference.
Operating Conditions
When StratixIII devices are implemented in a system, they are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of StratixIII devices, system designers must consider the operating requirements described in this chapter.
StratixIII devices are offered in both commercial and industrial grades. Commercial devices are offered in –2 (fastest), –3, –4, and –4L speed grades. Industrial devices are offered only in –3, –4, and –4L speed grades.
1
In this chapter, a prefix associated with the operating temperature range is attached to the speed grades; commercial with a “C” prefix and industrial with an “I” prefix. For example, commercial devices are indicated as C2, C3, C4, and C4L per respective speed grades. Industrial devices are indicated as I3, I4, and I4L.
Absolute Maximum Ratings
Absolute maximum ratings define the maximum operating conditions for StratixIII devices. The values are based on experiments conducted with the device and theoretical modeling of breakdown and damage mechanisms. The functional
operation of the device is not implied at these conditions. Conditions beyond those listed in Table1–1 may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods may have adverse effects on the device.
Table1–1.Absolute Maximum Ratings for StratixIII Devices(Note1)(Part 1 of 2)
SymbolVCCLVCCVCCD_PLLVCCA_PLLVCCPTVCCPGMVCCPDVCCIO
Parameter
Selectable core voltage power supplyI/O registers power supply
Phase-locked loop (PLL) digital power supplyPLL analog power supply
Programmable power technology power supplyConfiguration pins power supplyI/O pre-driver power supplyI/O power supply
Minimum-0.5-0.5-0.5-0.5-0.5-0.5-0.5-0.5
Maximum1.651.651.653.753.753.93.93.9
UnitVVVVVVVV
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Datasheet: DC and Switching Characteristics
Switching Characteristics
Table1–29.Transmitter Channel-to-Channel Skew (TCCS)—Write Side (Note1)(Part 2 of 2)
C2
Memory Type
I/O Standard
Width
VCCL = 1.1VTCCS (ps)Lead
QDRII/II+ SRAMQDRII/II+ SRAM Emulation (2) RLDRAM IIRLDRAM II
Notes to Table1–29:
(1)The values apply to Column I/Os, Row I/Os, and Hybrid mode interfaces. Column I/Os refer to top and bottom I/Os. Hybrid mode refers to DQ/DQS groups
wrapping over Column I/Os and Row I/Os of the device.(2)For implementation, refer to the “Supporting ×36 QDRII+/QDRII SRAM Interfaces in the F780 and F1152-Pin Packages” section in the External Memory
Interfaces in StratixIII Devices chapter.
C3, I3VCCL = 1.1VTCCS (ps)Lead260280292260
Lag385405388385
C4, I4VCCL = 1.1VTCCS (ps)Lead280300315280
Lag418438421418
C4L, I4LVCCL = 1.1VTCCS (ps)Lead280300315280
Lag418438421418
C4L, I4LVCCL = 0.9VTCCS (ps)Lead380400415380
Lag518538521518
Lag276296278276
1.8-V HSTL1.8-V HSTL1.5-V HSTL1.8-V HSTL
×9, ×18, ×36×36×9, ×18×9, ×18
259279290259
DLL and DQS Logic Block Specifications
Table1–30 lists the DLL frequency range specifications for StratixIII devices.
Table1–30.DLL Frequency Range Specifications for StratixIII DevicesFrequency Mode
01234567
Frequency Range (MHz)
C2 90 – 150120 – 200150 – 240180 – 300240 – 370290 – 450360 – 560470 – 740
C3, I390 – 140120 – 190150 – 230180 – 290240 – 350290 – 420360 – 530470 – 700
C4, I490 – 120120 – 170150 – 200180 – 250240 – 310290 – 370360 – 460470 – 610
C4L, I4L90 – 120120 – 170150 – 200180 – 250240 – 310290 – 370360 – 460470 – 610
Available Phase Shift22.5°, 45°, 67.5°, 90°30°, 60°, 90°, 120°36°, 72°, 108°, 144°45°, 90°,135°, 180°30°, 60°, 90°,120°36°, 72°, 108°, 144°45°, 90°, 135°, 180°60°, 120°, 180°, 240°
Number of Delay Chains
1612108121086
DQS Delay Buffer Mode (1)
LowLowLowLowHighHighHighHigh
Note to Table1–30:
(1)“Low” indicates a 6-bit DQS delay setting; “high” indicates a 5-bit DQS delay setting.
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Datasheet: DC and Switching CharacteristicsSwitching Characteristics
Table1–31 lists the average DQS phase offset delay per setting for StratixIII devices.Table1–31.Average DQS Phase Offset Delay per Setting for StratixIII Devices(Note1), (2), (3)Speed Grade
C2C3, I3C4, I4C4L, I4L
Notes to Table1–31:
(1)The valid settings for phase offset are -64 to +63 for frequency modes 0 to 3 and -32 to +31 for frequency modes
4 to 6.(2)The typical value equals the average of the minimum and maximum values.
(3)The delay settings are linear with a cumulative delay variation of ±20ps for all speed grades. For example, when
using a C2 speed grade and applying 10° phase offset settings to a 90° phase shift at 400 MHz, the expectedminimum cumulative delay is [625 ps + (10*7 ps) - 20 ps] = 675 ps.
Min7777
Typ101111.511.5
Max13151616
Unitpspspsps
Table1–32 lists the DQS phase shift error specification for DLL-delayed clock (tDQS_PSERR) for StratixIII devices.
Table1–32.DQS Phase Shift Error Specification for DLL-Delayed Clock (tDQS_PSERR) for StratixIII Devices(Note1)Number of DQS Delay
Buffer
1234
Note to Table1–32:
(1)This error specification is the absolute maximum and minimum error. For example, skew on three DQS delay buffers in a C2 speed grade is
±39ps.
C2±13±26±39±52
C3, I3 ±14±28±42±56
C4, C4L, I4, I4L
±15±30±45±60
Unitpspspsps
Table1–33 lists the memory output jitter specification for StratixIII devices.
Table1–33.Memory Output Clock Jitter Specification for StratixIII Devices(Note1), (2)
C2
Parameter
Clock NetworkRegionalRegionalRegionalGlobalGlobalGlobal
Symbol
VCCL = 1.1VMin
Clock period jitterCycle-to-cycle period jitterDuty cycle jitterClock period jitterCycle-to-cycle period jitterDuty cycle jitter
Notes to Table1–33:
(1)The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 standard.
(2)The clock jitter specification applies to memory output clock pins generated using differential signal-splitter and DDIO circuits clocked by a PLL output routed
on a regional or global clock network as specified. Altera recommends using the regional clock networks whenever possible.
C3, I3VCCL = 1.1VMin–85–170–90–128–255–135
Max8517090128255135
C4, I4VCCL = 1.1VMin Max–100–190–100–150–285–150
100190100150285150
C4L, I4L
VCCL = 1.1VMin Max–100–190–100–150–285–150
100190100150285150
VCCL = 0.9VMin Max–120–230–140–180–340–180
120230140180340180
pspspspspspsUnit
Max7515080113225120
tJIT(per)tJIT(cc)tJIT(duty)tJIT(per)tJIT(cc)
–75–150–80–113–225
tJIT(duty)–120
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Datasheet: DC and Switching Characteristics
I/O Timing
OCT Calibration Block Specifications
Table1–34 lists the on-chip termination calibration block specifications for StratixIII devices.
Table1–34.On-Chip Termination Calibration Block Specification
SymbolOCTUSRCLKtOCTCALtOCTSHIFTtRS_RT
Description
Clock required by OCT calibration blocks Number of OCTUSRCLK clock cycles required for OCT Rs and Rt calibration
Number of OCTUSRCLK clock cycles required for OCT code to shift out per OCT calibration blockTime required to dynamically switch from Rs to Rt
Min————
Typical—1000282.5
Max20———
UnitMHzcyclescyclesns
DCD Specifications
Table1–35 lists the worst case duty cycle distortion for StratixIII devices. Table1–35.Duty Cycle Distortion on StratixIII I/O Pins(Note1)
Symbol
Min
Output Duty Cycle
Note to Table1–35:
(1)The DCD specification applies to clock outputs from the PLLs, global clock tree, and IOE driving dedicated and
general-purpose I/O pins.
C2Max55
Min45
C3Max55
Min45
C4Max55
Unit%
45
I/O Timing
The following sections describe the timing models, preliminary and final timings, I/O timing measurement methodology, I/O default capacitive loading, programmable IOE delay, programmable output buffer delay, user I/O timing, and dedicated clock pin timing.
Timing Model
The DirectDrive technology and MultiTrack interconnect ensure predictable
performance, accurate simulation, and accurate timing analysis across all StratixIII device densities and speed grades. This section describes the performance of the StratixIII device I/Os.
All specifications except the fast model are representative of worst-case supply voltage and junction temperature conditions. Fast model specifications are representative of best case process, supply voltage, and junction temperature conditions.
The timing numbers listed in this section are extracted from the QuartusII software version 8.1.
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Datasheet: DC and Switching CharacteristicsI/O Timing
Stratix III Device Handbook, Volume 2
FPGA可编程逻辑器件芯片EP1S20F484C5中文规格书 - 图文
