SIII52001-2.1
Electrical Characteristics
Operating Conditions
When Stratix?III devices are implemented in a system, they are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of StratixIII devices, system designers must consider the operating requirements discussed in this chapter. StratixIII devices are offered in both
commercial and industrial grades. Commercial devices are offered in –2 (fastest), –3, –4 and –4L speed grades. Industrial devices are offered only in –3, –4, and –4L speedgrades.
1
In this chapter, a prefix associated with the operating temperature range is attached to the speed grades; commercial with “C” prefix and industrial with “I” prefix.
Commercial devices are therefore indicated as C2, C3, C4, and C4L per respective speed grades. Industrial devices are indicated as I3, I4, and I4L.
Absolute Maximum Ratings
Absolute maximum ratings define the maximum operating conditions for StratixIII devices. The values are based on experiments conducted with the device and theoretical modeling of breakdown and damage mechanisms. The functional
operation of the device is not implied at these conditions. Conditions beyond those listed in Table1–1 may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods may have adverse effects on the device.
Table1–1.StratixIII Device Absolute Maximum Ratings (Note1)(Part 1 of 2)
SymbolVCCLVCCVCCD_PLLVCCA_PLLVCCPTVCCPGMVCCPDVCCIOVCC_CLKINVCCBATVI
Parameter
Selectable core voltage power supplyI/O registers power supplyPLL digital power supplyPLL analog power supply
Programmable power technology power supplyConfiguration pins power supplyI/O pre-driver power supplyI/O power supply
Differential clock input power supply (top and bottom I/O banks only)
Battery back-up power supply for design security volatile key registerDC Input voltage
Minimum-0.5-0.5-0.5-0.5-0.5-0.5-0.5-0.5-0.5-0.5-0.5
Maximum1.651.651.653.753.753.93.93.93.753.754.0
UnitVVVVVVVVVVV
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics
Switching Characteristics
Table1–22.StratixIII TriMatrix Memory Block Performance Specifications (Note1)(Part 3 of 3)Memory Block Type
M144K (3), (5)
Mode
Simple dual-port 2K × 64 (with ECC)Min Pulse Width (Clock High Time)Min Pulse Width (Clock Low Time )
TriMatrix
ALUTs
Memory
0——
1——
C2 (6)VCCL = 1.1V
255800500
C3C4C4LI3VCCL=1.1V
1951000625
I4VCCL=1.1V
1801100690
I4LVCCL=0.9V
12018001100
VCCL = VCCL = VCCL = VCCL = 1.1V1.1V1.1V0.9V
2101000625
1801100690
1801100690
13018001100
Unit
MHzpsps
Notes to Table1–22:
(1)Use a memory block clock that comes through global clock routing from an on-chip PLL set to 50% output duty cycle to achieve the maximum memory block
performance. Use Quartus II software to report timing for this and other memory block clocking schemes.(2)The Fmax shown for M9K degrades 2 % when you use Error Detection CRC feature on the device, except for C4L speed grade with VCCL=0.9 V. For C4L speed
grade with VCCL=0.9V, there is no degradation in Fmax when Error Detection CRC feature is used.(3)The Fmax shown for M144K degrades 10 MHz when you use byte-enable support on M144K.(4)The Fmax is applicable when the COMPTABILITY option is turned ON.
(5)The Fmax is applicable when the COMPTABILITY option is turned OFF. This option is turned ON by default in QuartusII software.(6)The Fmax for EP3SL200, EP3SE260, and EP3SL340 at C2 Speed Grade is 7% slower than the C2 values shown in the table.
Configuration and JTAG Specifications
Table1–23 lists the StratixIII Configuration Mode Specifications.Table1–23.StratixIII Configuration Mode Specifications (Note1)
Programming Mode
Passive SerialFast Passive Parallel (2)Fast Active Serial (3)
Notes to Table1–23:
(1)DCLK Fmax is restricted when Remote Update is enabled. For more information, refer to Remote Update Circuitry
(ALTREMOTE_UPDATE) Megafunction User Guide.(2)Data rate must be 4× slower than the clock when decompression and/or encryption are used.
(3)For more information about the minimum and typical DCLK Fmax value in Fast Active Serial configuration, refer to
the Serial Configuration Devices Data Sheet chapter in Cyclone Device Handbook.
DCLK Fmax
10010040
UnitMHzMHzMHz
Table1–24 shows the JTAG timing parameters and values for StratixIII devices. Refer to figure for “HIGH-SPEED I/O Block” in “Glossary” for JTAG timing requirements.Table1–24.StratixIII JTAG Timing Parameters and Values
SymboltJCPtJCHtJCL
tJPSU (TDI)tJPSU (TMS) tJPHtJPCOtJPZXtJPXZ
Parameter
TCK clock periodTCK clock high timeTCK clock low timeJTAG port setup time for TDIJTAG port setup time for TMSJTAG port hold timeJTAG port clock to output
JTAG port high impedance to valid outputJTAG port valid output to high impedance
Min301414135———
Max——————11 14 14
Unitnsnsnsnsnsnsnsnsns
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching CharacteristicsSwitching Characteristics
Periphery Performance
This section describes periphery performance, including high-speed I/O and external memory interface.
I/O performance supports several system interfacing, such as the LVDS high-speed I/O interface, external memory interface, and the PCI/PCI-X bus interface. For
example, StratixIII devices I/O configured with voltage referenced I/O standards can achieve up to the stated system interfacing speed as indicated in “External Memory Interface Specifications” on page1–25. General-purpose I/O standards such as 3.3, 3.0, 2.5, 1.8, or 1.5 LVTTL/LVCMOS are capable of typical 167 MHz and 1.2LVCMOS at 100MHz interfacing frequency with 10pF load.
1
Actual achievable frequency depends on design- and system-specific factors. You should perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
High-Speed I/O Specifications
Refer to the “Glossary” for definitions of high-speed timing specifications.Table1–25 shows the high-speed I/O timing for StratixIII devices.
Table1–25.True & Emulated LVDS Specifications(Note1), (2)(Part 1 of 3)
Symbol
fHSCLK_in
(input clockfrequency)fHSCLK_out
(output clockfrequency)Transmitter
MaxMaxMaxClock boost
factor W = 1 to 40 (3)
?—800?—717?—717?—717
MaxMinMinMinMinTypTypTypTypConditions
MHz
—5—800 (7)5—717 (7)5—717 (7)5—717 (7)MHz
SERDES factor J = 3 to 10 (8)
fHSDR (data rate)
(4)(4)
——
1600(4)
(4)(4)
——
1250(4)
(4)(4)
——
1250(4)
(4)(4)
——
1250(4)
MbpsMbps
SERDES factorJ = 2, Uses DDR RegisterSERDES factorJ = 1, Uses SDR Register
(4)(4)(4)
———
(4)1100311
(4)(4)(4)
———
(4)1100200
(4)(4)(4)
———
(4)800200
(4)(4)(4)
———
(4)800200
MbpsMbpsMbps
LVDS_E_3R -fHSDR (data rate)LVDS_E_1R -fHSDR (data rate)
SERDES factorJ = 4 to 10SERDES factor J = 4 to 10
Stratix III Device Handbook, Volume 2
UnitC2C3, I3C4, I4C4L, I4L
Chapter 1:StratixIII Device Data Sheet: DC and Switching CharacteristicsI/O Timing
Table1–39.Output Timing Measurement Methodology for Output Pins(Part 3 of 3)
I/O Standard
RS
MINI-LVDS_E_1RMINI-LVDS_E_3RRSDS_E_1RRSDS_E_3R
Notes to Table1–39:
(1)Hyper transport is not supported by StratixIII.(2)LVPECL outputs are not supported by StratixIII.
(3)Quartus timing conditions can be changed using the Advanced I/O Timing feature.(4)VCC is nominally 1.1 V less 50 mV (1.05 V).
(5)Terminated I/O standards require an additional 30 mV IR drop on VCC (1.02 V).(6)Terminated I/O standards required an additional 50 mV IR drop on VCCIO and VCCPD.
Loading and Terminations
RD100100100100
RT————
RP120170120170
VCCIO2.3252.3252.3252.325
VCCPD2.3252.3252.3252.325
VCC1.021.021.021.02
VTT————
CL (pF)0000
Measurement
PointVMEAS (v)1.16251.16251.16251.1625
—120—120
I/O Default Capacitive Loading
See Table1–40 for default capacitive loading of different I/O standards.Table1–40.Default Loading of Different I/O Standards for StratixIII (Part 1 of 2)
I/O Standard
3.3-V LVTTL3.3-V LVCMOS3.0-V LVTTL3.0-V LVCMOS2.5-V LVTTL/LVCMOS1.8-V LVTTL/LVCMOS1.5-V LVTTL/LVCMOS3.0-V PCI3.0-V PCI-XSSTL-2 CLASSISSTL-2 CLASSIISSTL-18 CLASSISSTL-18 CLASSII1.5-V HSTL CLASSI1.5-V HSTL CLASSII1.8-V HSTL CLASSI1.8-V HSTL CLASSII1.2-V HSTL
Differential SSTL-2 CLASSIDifferential SSTL-2 CLASSIIDifferential SSTL-18 CLASSI
Capacitive Load
00000001010000000000000
UnitpFpFpFpFpFpFpFpFpFpFpFpFpFpFpFpFpFpFpFpFpF
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching CharacteristicsI/O Timing
Stratix III Device Handbook, Volume 2
FPGA可编程逻辑器件芯片EP4SGX230FF35I3N中文规格书 - 图文
