Chapter1
VC707 Evaluation Board Features
Overview
The VC707 evaluation board for the Virtex?-7FPGA provides a hardware environment for developing and evaluating designs targeting the Virtex-7 XC7VX485T-2FFG1761C FPGA. The VC707 board provides features common to many embedded processing systems, including a DDR3 SODIMM memory, an 8-lane PCI Express? interface, a tri-mode Ethernet PHY, general purpose I/O, and two UART interfaces. Other features can be added by using mezzanine cards attached to either of two VITA-57 FPGA mezzanine connectors (FMC) provided on the board. Two high pin count (HPC) FMCs are provided. See VC707 Board Features for a complete list of features. The details for each feature are described in Feature Descriptions.
Additional Information
See AppendixG, Additional Resources for references to documents, files and resources relevant to the VC707 board.
VC707 Board Features
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Virtex-7 XC7VX485T-2FFG1761C FPGA1GB DDR3 memory SODIMM
128MB Linear byte peripheral interface (BPI) Flash memoryUSB 2.0 ULPI TransceiverSecure Digital (SD) connectorUSB JTAG through Digilent moduleClock Generation?????
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Fixed 200MHz LVDS oscillator (differential)I2C programmable LVDS oscillator (differential)SMA connectors (differential)
SMA connectors for GTX transceiver clockingFMC1 HPC connector (eight GTX transceivers)FMC2 HPC connector (eight GTX transceiver)
SMA connectors (one pair each for TX, RX, and REFCLK)PCI Express (eight lanes)
Small form-factor pluggable plus (SFP+) connectorEthernet PHY SGMII interface (RJ-45 connector)
GTX transceivers
VC707 Evaluation Board
UG885 (v1.8) February 20, 2019
Chapter 1:VC707 Evaluation Board Features
User LEDs
Figure1-23 shows the user LED circuits.
X-Ref Target - Figure 1-23GPIO_LED_0GPIO_LED_1GPIO_LED_2GPIO_LED_3GPIO_LED_4GPIO_LED_5GPIO_LED_6GPIO_LED_7DS9DS8DS7DS6DS5DS4DS3DS2R15449.9Ω1%R15349.9Ω1%R15249.9Ω1%R15149.9Ω1%R15049.9Ω1%R14949.9Ω1%R14849.9Ω1%R14749.9Ω1%GNDUG855_c1_23_020612Figure 1-23:User LEDs
CPU Reset Pushbutton
Figure1-24 shows the CPU reset pushbutton switch circuit.
X-Ref Target - Figure 1-24VCC1V8SW8CPU_RESET4312R414.7kΩ0.1W5%GNDUG885_c1_123_012513Figure 1-24:CPU Reset Pushbutton
VC707 Evaluation BoardUG885 (v1.8) February 20, 2019
Feature Descriptions
VC707 Evaluation Board
UG885 (v1.8) February 20, 2019
Chapter 1:VC707 Evaluation Board Features
VC707 Evaluation BoardUG885 (v1.8) February 20, 2019
Feature Descriptions
Table1-32 defines the voltage and current values for each power rail controlled by the UCD9248 PMBus controller at address 54 (U64).
Table 1-32:
Power Rail Specifications for UCD9248 PMBus Controller at Address 54
Shutdown Threshold(1)
IOUT Over Fault (A)Temp Over Fault (°C)90909090
VOUT Over Fault (V)2.31.152.072.07
Nominal VOUT (V)PGOff Threshold (V)PGOn Threshold (V)Rise Time (ms)Off Delay (ms)On Delay (ms)RailNumberRailNameSchematicRail Name
1234
Rail #1Rail #2Rail #3Rail #4
VCCAUX_IOVCC_BRAMMGTVCCAUXVCC1V8_FPGA
211.81.8
1.80.91.621.62
1.70.851.531.53
0000
5555
2975
Fall Time (ms)1111
10.4110.4110.4110.41
Notes:
1.The values defined in these columns are the voltage, current, and temperature thresholds that cause the regulator to shut down if the value isexceeded.
FPGA Cooling Fan Operation
The FPGA cooling fan control circuit has its PWM signal wired to a dual-use FPGA Bank15 pin BA37. After configuration, this pin is expected to be toggled by user-provided fan speed control IP to control fan speed.
FPGA U1 pin BA37 is alternately an unused BPI flash memory address pin (A28). During FPGA configuration in BPI mode, the BPI flash memory address lines are driven. The BA37 pin is held low during BPI configuration and thus the fan PWM signal is not active. The FPGA U1 cooling fan is off during the FPGA BPI configuration process.
After configuration is complete, the dual-use FPGA pin BA37 is available for use by user-provided fan speed control IP.
References
More information about the power system components used by the VC707 board are available from the Texas Instruments digital power website [Ref25].
PCIe Form Factor Board TI Power System Cooling
If the power modules on the VC707 board are operating at moderate to high current levels (due to a customer design), the modules can generate substantial heat, which can cause them to shut down without warning. The power module shutdown then turns off the FPGA on the development board. Refer to the Virtex-7FPGA VC707 Evaluation Kit Master Answer Record in AppendixG: References for more information.
VC707 Evaluation Board
UG885 (v1.8) February 20, 2019
FPGA可编程逻辑器件芯片XC2S150-6FG256I中文规格书 - 图文
