State Machine Design with Memories??Recall 101 sequence detector??Mealy machineNSPSx=0x=1ABA+B+A+B+00000,001,010110,001,021000,001,1March 12, 2012ECE 152A -Digital Design Principles21State Machine Design with Memories??ROM Contents (8 x 3-bit)AddressDataPSxNSz000000001010010100011010100000101011110xxxx111xxxxMarch 12, 2012ECE 152A -Digital Design Principles2211State Machine Design with Memories??Timing DiagramMarch 12, 2012ECE 152A -Digital Design Principles23State Machine Design with Memories??101 sequence detector (again)??Moore machineNSPSx=0x=1ABA+B+A+B+Z00000010101100102100011031110011March 12, 2012ECE 152A -Digital Design Principles2412State Machine Design with Memories??Direct mapping of state table to memory??Output lags by one clock period??Introduces latency to output timing??“Pipelining”effect??Implement as “Mealy-like”machine??Associate output with next state, not present state??All states have only one associated output (like Moore)??Eliminates one clock-period latency??No longer “true”Moore machineMarch 12, 2012ECE 152A -Digital Design Principles2513
电子电路 L13- RAM& ROM Based Digital Design(1) - 图文
