Read Only Memories??ROM, PROM, EPROM, EEPROM, EAROM??EEPROM : Electrically Erasable Programmable Read Only Memory??Programmed by user??Erased electrically ??Possibly in system, but requires non-standard voltages??EAROM : Electrically Alterable Read Only Memory??Similar to EEPROMMarch 12, 2012ECE 152A -Digital Design Principles11Read Mostly Memories??Flash memory??Writable and non-volatile??Reads very fast??Writes very slowly??Referred to as “programming”??No special voltages for in system writing??“Flash”refers to the fact that the entire content of the memory chip can be erased in one step??Once erased and written, data is retained for 20+ yearsMarch 12, 2012ECE 152A -Digital Design Principles126Memory Structure??Array of memory cells??Organization refers to number of and width of memory words??Example 1024 bit memory can organized as:??1024 one-bit word??512 two-bit words??256 four-bit words??128 eight-bit words??Internal array is the same for all organizations??Decoding and I/O circuitry differsMarch 12, 2012ECE 152A -Digital Design Principles13Memory Structure??Memory Array and Address DecoderMarch 12, 2012ECE 152A -Digital Design Principles147Combinational Design with Memories??ROM (and RAM and Flash) is a “physical”truth table??All addresses equal ≡all inputs to logic network??Each row of truth table corresponds to a single address in the memory??Example: 128 x 8 ROM??128, 8-bit words??Log2128 = 7 address bits (A6 –A0)??8 data bits D7 –D0??Can implement 7 input, 8 output functionMarch 12, 2012ECE 152A -Digital Design Principles15Combinational Design with Memories??Binary to BCD converter with 128 x 8-bit ROM??Addresses 0 –99??Output equals 2 digit BCD number??Addresses 100 –127??All one’s, indicating invalid inputMarch 12, 2012ECE 152A -Digital Design Principles168Combinational Design with Memories??ROM Contents??Hex addresses 00 through 7FAddressDataDecimal Value000000 000000010000 0001010F0001 010115100001 011016631001 100199641111 1111Invalid7F1111 1111InvalidMarch 12, 2012ECE 152A -Digital Design Principles17Combinational Design with Memories??Final ImplementationMarch 12, 2012ECE 152A -Digital Design Principles189State Machine Design with Memories??For state machine, map state table directly into memory??Address lines driven by present state and present input??Data outputs consist of next state and present output??Both Mealy and Moore machines can be realized??Output of Moore machine lags by one clock period (when state table directly mapped) March 12, 2012ECE 152A -Digital Design Principles19State Machine Design with Memories??Hardware ImplementationMarch 12, 2012ECE 152A -Digital Design Principles2010
电子电路 L13- RAM& ROM Based Digital Design(1) - 图文
