This section includes the following chapters:
■■
Chapter1, DC and Switching Characteristics for Stratix IV DevicesChapter2, Addendum to the Stratix IV Device Handbook
Revision History
Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook.
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1:DC and Switching Characteristics for Stratix IV DevicesElectrical Characteristics
Table1–6.Recommended Operating Conditions for Stratix IV Devices (Part 2 of 2)
Symbol
Description
ConditionNormal POR (PORSEL=0)Fast POR (PORSEL=1)
Minimum0.050.05
Typical——
Maximum
Unit
100 ms4 mstRAMP
Power supply ramp time
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1:DC and Switching Characteristics for Stratix IV DevicesElectrical Characteristics
Table1–21.Differential HSTL I/O Standards I/O StandardHSTL-18 Class IHSTL-15 Class I, IIHSTL-12 Class I, II
VCCIO (V)Min1.711.4251.14
Typ1.81.51.2
Max1.891.5751.26
VDIF(DC) (V)Min0.20.20.16
Max——VCCIO +0.3
Min0.780.68—
VX(AC) (V)Typ——0.5* VCCIO
Max1.120.9—
Min0.780.680.4* VCCIO
VCM(DC) (V)Typ——0.5* VCCIO
Max1.120.90.6* VCCIO
VDIF(AC) (V)Min0.40.40.3
Max——VCCIO +0.48
Table1–22.Differential I/O Standard Specifications (1), (2)(Part 1 of 2)I/O StandardPCML
VCCIO (V)(3)Min
Typ
Max
VID (mV)
MinConditionMaxMin
VICM(DC) (V)Condition
Max
VOD (V) (4)Min
TypMax
Min
VOCM (V) (4)
Typ
Max
Transmitter, receiver, and input reference clock pins of high-speed transceivers use PCML I/O standard. For transmitter, receiver, and reference clock I/O pin specifications, refer to Table1–23 on page1–16 and Table1–24 on
page1–25.
VCM = 1.25V
——————600600——
0.05
(5)
2.5V LVDS
2.3752.52.625100
(HIO)
DMAX ? 700Mbps
1.8
(5)
0.247————0.20.2————
0.60.60.60.60.60.60.60.6——
1.1251.251.3751.1251.251.375110.50.511——
1.251.251.21.21.21.2——
1.51.51.41.51.41.5——
1.05
(5)
DMAX > 1.55(
0.2475)700MbpsDMAX ?
700MbpsDMAX> 700Mbps————DMAX ? 700MbpsDMAX > 700Mbps
1.8 0.2471.55 0.2471.41.41.3251.3251.8
(6)
2.5V LVDS
2.3752.52.625100
(VIO)RSDS (HIO)RSDS (VIO)Mini-LVDS (HIO)Mini-LVDS (VIO)
VCM = 1.25VVCM = 1.25VVCM = 1.25V————
0.05 1.05 0.30.30.40.40.6
(6)
2.3752.52.6251002.3752.52.6251002.3752.52.6252002.3752.52.6252002.3752.52.625300
0.10.10.250.25——
LVPECL(7)
2.3752.52.625300
1
(6)
1.6
(6)
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1:DC and Switching Characteristics for Stratix IV DevicesSwitching Characteristics
Table1–24.Transceiver Specifications for Stratix IV GT Devices(Part 6 of 8)
Symbol/Description
ConditionsPCIe Gen1 and Gen2 (TX VOD=4),XAUI (TX VOD=6),HiGig+ (TX VOD=6),CEI SR/LR (TX VOD=8),Serial RapidIO SR (VOD=6),Serial RapidIO LR (VOD=8),CPRI LV (VOD=6),CPRI HV (VOD=2),OBSAI (VOD=6),SATA (VOD=4),
—————×4 PMA and PCS bonded mode Example: XAUI, PCIe, ×4, Basic×4×8 PMA and PCS bonded mode Example: PCIe×8, Basic×8
50506060—
—————
20020013013015
50506060—
–1 Industrial Speed
GradeMin
Typ
Max
–2 Industrial Speed
GradeMin
Typ
Max
–3 Industrial Speed
Grade Min
Typ
Max
Unit
Differential and common mode return loss
Compliant—
Rise time (13)Fall time (13)XAUI rise timeXAUI fall timeIntra-differential pair skew
Intra-transceiver block transmitter channel-to-channel skew
Inter-transceiver block transmitter channel-to-channel skew
—————
20020013013015
50506060—
—————
20020013013015
pspspspsps
——120——120——120ps
——500——500——500ps
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1:DC and Switching Characteristics for Stratix IV DevicesSwitching Characteristics
Table1–24.Transceiver Specifications for Stratix IV GT Devices(Part 7 of 8)
Symbol/Description
ConditionsN < 18 channels located across
three transceiver blocks with the source CMU PLL located in the center transceiver blockN ? 18 channels located across four transceiver blocks with the source CMU PLL located in one of the two
center transceiver blocks
–1 Industrial Speed
GradeMin
Typ
Max
–2 Industrial Speed
GradeMin
Typ
Max
–3 Industrial Speed
Grade Min
Typ
Max
Unit
——400——400——400ps
Inter-transceiver block skew in Basic (PMA Direct) ×N mode (14)
——650——650——650ps
CMU PLL0 and CMU PLL1Supported data range
CMU PLL lock time from
pll_powerdown de-assertionATX PLL (6G)
/L = 1
Supported Data Range
/L = 2/L = 4
ATX PLL (10G)Supported Data Range
—
9900
—
11300
9900
—
10312.5
—
Mbps
4800-5400 and 6000-65002400-2700 and 3000-32501200-1350 and 1500-1625
4800-5400 and 6000-65002400-2700 and 3000-32501200-1350 and 1500-1625
4800-5400 and 6000-65002400-2700 and 3000-32501200-1350 and1500-1625
MbpsMbpsMbps
—
600
—
11300
600
—
10312.5
600
—
8500
Mbps
———100——100——100?s
Transceiver-FPGA Fabric InterfaceInterface speed(non-PMA Direct)Interface speed(PMA Direct)
——
2550
——
325325
2550
——
325 25325
50
——
265.625325
MHzMHz
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
FPGA可编程逻辑器件芯片EP4SGX180KF40I3N中文规格书 - 图文
