Carnegie MellonThe Memory Hierarchy
Brad Karp
UCL Computer Science
CS 3007
30thJanuary 2018
(lecture notes derived from material from Phil Gibbons, Randy
Bryant, and Dave O’Hallaron)
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Today
￠Storage technologies and trends￠Locality of reference
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Caching in the memory hierarchy
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Random-Access Memory (RAM)
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Key features
§RAM is traditionally packaged as a chip.
§Basic storage unit is normally a cell (one bit per cell).§Multiple RAM chips form a memory.
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RAM comes in two varieties:
§SRAM (Static RAM)§DRAM (Dynamic RAM)
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Carnegie MellonSRAM vsDRAM SummaryTrans.per bitSRAMDRAM61AccessNeedstimerefresh?Cost1X10XNoYes100x1XApplicationsCache memoriesMain memories,frame buffers4Carnegie MellonEnhanced DRAMs
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Basic DRAM cell has not changed since its invention in 1966.
§Commercialized by Intel in 1970.
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DRAM cores with better interface logic and faster I/O :
§Synchronous DRAM (SDRAM)
§§
Uses a conventional clock signal instead of asynchronous controlAllows reuse of the row addresses (e.g., RAS, CAS, CAS, CAS)
§Double data-rate synchronous DRAM (DDR SDRAM)
§§§§
Double-edge clocking sends two bits per cycle per pin
Different types distinguished by size of small prefetchbuffer:–DDR(2 bits), DDR2(4 bits), DDR3(8 bits)
By 2010, standard for most server and desktop systemsIntel Core i7 supports DDR3 and DDR4 SDRAM
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伦敦大学学院-计算机系统 (7)
