74HC595PW TI运算放大器 - 图文 

74HC595PW是一款具有8位移位寄存器和一个存储器，三态输出功能的驱动芯片。移位寄存器和存储器分别具有独立的时钟信号。数据在SHCP的上升沿输入，在STCP的上升沿进入到存储寄存器中去。

如果两个时钟连在一起，则移位寄存器总是比存储寄存器早一个脉冲。移位寄存器有一个串行移位输入（DS），和一个串行输出（Q7’），和一个异步的低电平复位（MR），存储寄存器有一个并行8位的，具备三态的总线输出，当使能OE时（为低电平），存储寄存器的数据输出到总线。

FEATURES · 8位串行输入 · 8位串行或并行输出 · 带三态输出的存储寄存器 · 移位寄存器直接清除 · 100 MHz（典型）移出频率 ·? ESD防护：

DESCRIPTION

74HC / HCT595是高速Si-gate CMOS器件，并且与低功耗肖特基TTL（LSTTL）引脚兼容。 它们的指定符合JEDEC标准No. 7A。

74HC / HCT595是具有存储寄存器和三态输出的8级串行移位寄存器。 移位寄存器和存储寄存器具有独立的时钟。

数据在SH_CP输入的正向跃迁上移动。 在ST_CP输入的正向转换时，每个寄存器中的数据都会传输到存储寄存器。 如果两个时钟都连接在一起，则移位寄存器将始终比存储寄存器早一个时钟脉冲。

移位寄存器具有用于级联的串行输入（DS）和串行标准输出（Q7’）。 它还为所有8个移位寄存器级提供了异步复位（低电平有效）。 存储寄存器具有8个并行3状态总线驱动器输出。 每当输出使能输入（OE）为低电平时，存储寄存器中的数据就会出现在输出上。

CONDITIONS HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V.?

APPLICATIONS · S串并数据转换 · 遥控器保持寄存器。

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 ?C; tr = tf = 6 ns. SYMBOL PARAMETER TYPICAL 74HC 74HCT UNIT tPHLPLH /t propagation delay SH_CP to Q7’ CL = 50 pF; VCC = 4.5 V 19 20 100 25 24 52 ns ns ns SH_CP to Qn fmax CI CPD

Notes

MR to Q7’ maximum clock frequency SH_CP and ST_CP input capacitance power dissipation capacitance per package notes 1 and 2 100 3.5 115 57 3.5 130 MHz pF pF 1. CPD is used to determine the dynamic power dissipation (PD in mW). PD = CPD ? VCC2 ? fi ? N + S(CL ? VCC2 ? fo) where:

fi = input frequency in MHz; fo = output frequency in MHz;

CL = output load capacitance in pF; VCC = supply voltage in Volts;

N = total load switching outputs;

2

S(CL ? VCC ? fo) = sum of the outputs.

2. For 74HC595 the condition is VI = GND to VCC.

For 74HCT595 the condition is VI = GND to VCC - 1.5 V.

FUNCTION TABLE See note 1.

INPUT OUTPUT FUNCTION SH_CP ST_CP OE MR DS Q7’ Qn n.c. L Z n.c. X X X ? X ? X X L L H L L L L X X X H L L L Q6’ a LOW level on MR only affects the shift registers empty shift register loaded into storage register shift register clear; parallel outputs in high-impedance OFF-state logic high level shifted into shift register stage 0; contents of all shift register stages shifted through, e.g. previous state of stage 6 (internal Q6’) appears on the serial output (Q7’) H X ? L H X n.c. Qn’ contents of shift register stages (internal Qn’) are transferred to the storage register and parallel output stages contents of shift register shifted through; previous contents of the shift register is transferred to the storage register and the parallel output stages ? ? L H X Q6’ Qn’ Note

1. H = HIGH voltage level;

L = LOW voltage level;

? = LOW-to-HIGH transition; ? = HIGH-to-LOW transition;?Z = high-impedance OFF-state; n.c. = no change;

X = don’t care.

ORDERING INFORMATION PACKAGE PINS PACKAGE TYPE NUMBER TEMPERATURE RANGE MATERIAL CODE 74HC595N ?40 to +125 ?C 16 DIP16 plastic SOT38-4 SOT38-4 74HCT595N ?40 to +125 ?C 16 DIP16 plastic plastic 74HC595D ?40 to +125 ?C 16 SO16 SO16 SOT109-1 SOT109-1 74HCT595D ?40 to +125 ?C 16 16 plastic plastic 74HC595DB ?40 to +125 ?C ?40 to +125 ?C SSOP16 SSOP16 SOT338-1 SOT338-1 74HCT595DB 16 16 plastic plastic 74HC595PW ?40 to +125 ?C ?40 to +125 ?C TSSOP16 TSSOP16 SOT403-1 SOT403-1 74HCT595PW 16 16 plastic plastic 74HC595BQ ?40 to +125 ?C ?40 to +125 ?C DHVQFN16 DHVQFN16 SOT763-1 SOT763-1 74HCT595BQ 16 plastic

PIN

SYMBOL DESCRIPTION parallel data output 1 2 3 4 5 6 7 8 9 Q1 Q2 Q3 Q4 Q5 Q6 Q7 GND Q7’ parallel data output parallel data output parallel data output parallel data output parallel data output parallel data output ground (0 V) serial data output 10 11 MR SH_CP master reset (active LOW) shift register clock input 12 ST_CP storage register clock input 13 14 OE DS output enable (active LOW) serial data input 15 16 Q0 Vparallel data output CC positive supply voltage handbook, halfpage handbook, halfpage Q1 1 Q2 2 Q3 3 2 3 4 Q1 1 VCC 16 15 Q0 14 DS 13 OE 16 VCC Q2 Q3 Q4 15 Q0 14 DS 13 OE Q4 4 Q5 5 Q6 6 Q7 7 GND 8 595 12 ST_CP Q5 Q6 Q7 5 6 7 GND (1) 12 ST_CP 11 SH_CP 10 MR 11 SH_CP 9 Q7' 10 MR 8 9 Q7' GND MLA001 Top view MBL893 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig.1 Pin configuration DIP16, SO16 and (T)SSOP16. Fig.2 Pin configuration DHVQFN16.

handbook, halfpage 11 12 handbook, halfpage OE SH_CP ST_CP 9 15 1 Q7' Q0 Q1 Q2 ST_CP SH_CP 13 EN3 12 10 11 R C2 MR C1/ SRG8 2 DS 14 1D 2D 3 15 14 DS Q3 Q4 3 4 5 1 2 Q0 Q1 Q5 Q6 Q7 6 7 Q2 3 Q3 4 Q4 5 Q5 6 Q6 MR OE 7 9 Q7 10 13 MLA002 MSA698 Q7' Fig.3 Logic symbol. Fig.4 IEC logic symbol. 14 DS 10 MR 11 SH_CP 8-STAGE SHIFT REGISTER Q7' 9 12 ST_CP 8-BIT STORAGE REGISTER Q0 Q1 Q3 15 13 OE Q2 2 1 3 4 5 3-STATE OUTPUTS Q4 Q5 Q6 6 Q7 7 Fig.5 Functional diagram. MLA003

handbook, full pagewidth

STAGE 0 D

Q

STAGES 1 to 6 D

Q

STAGE 7 D

Q

DS Q7'

FF0

CP R

SH_CP MR

FF7 CP R

D CP

Q

D CP

Q

LATCH LATCH

ST_CP

OE

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

MLA010

Fig.6 Logic diagram.

SH_CP

DS

ST_CP

MR

OE

Q0

high-impedance OFF-state

Q1

Q6

Q7

Q7'

MLA005-1

Fig.6 Timing diagram.

RECOMMENDED OPERATING CONDITIONS

SYMBOL

PARAMETER CONDITIONS 74HC MIN. TYP. 74HCT MAX. MIN. TYP. MAX. 5.5 UNIT VCC supply voltage input voltage output voltage ambient temperature input rise and fall time VI VO Tamb VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 2.0 0 0 ?40 ? ? ? 5.0 ? ? ? ? 6.0 ? 6.0 VCC VCC +125 1000 500 400 4.5 0 0 ?40 ? ? ? 5.0 ? ? ? ? 6.0 ? VCC VCC +125 ? 500 ? V V V ?C ns ns ns tr, tf

LIMITED VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC supply voltage ?0.5 +7.0 V IIK VI < ?0.5 V to VI > VCC + 0.5 V input diode current ? ?20 mA IOK VO < ?0.5 V to VO > VCC + 0.5 V output diode current ? ?20 mA IO VO = ?0.5 V to VCC + 0.5 V output source or sink current Q7’ standard output ? ?25 mA Qn bus driver outputs ? ?35 mA I, ICCGND VCC or GND current ? ?70 mA Tstg storage temperature ?65 +150 ?C PTamb = ?40 to +125 ?C; note 1 tot power dissipation ? 500 mW Note

1. For DIP16 packages: above 70 ?C derate linearly with 12 mW/K.

For SO16 packages: above 70 ?C derate linearly with 8 mW/K.

For SSOP16 packages: above 60 ?C derate linearly with 5.5 mW/K. For TSSOP16 packages: above 60 ?C derate linearly with 5.5 mW/K. For DHVQFN16 packages: above 60 ?C derate linearly with 4.5 mW/K.

DC CHARACTERISTICS

Type 74HC

TEST CONDITIONS

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).74HC595PW SYMBOL PARAMETER OTHER VCC (V) MIN. TYP. MAX. UNIT Tamb = ?40 to +85 ?C; note 1 VIH HIGH-level input voltage V 2.0 4.5 1.5 3.15 1.2 2.4 ? ? V V V 6.0 4.2 3.2 ? 0.5 1.35 IL LOW-level input voltage 2.0 4.5 ? ? 0.8 2.1 2.8 V V V V 6.0 ? 1.8 OH HIGH-level output voltage VI = VIH or VIL all outputs IO = ?20 ?A 2.0 4.5 6.0 1.9 4.4 5.9 2.0 4.5 6.0 ? ? ? V V V Q7’ standard output IO = ?4.0 mA IO = ?5.2 mA Qn bus driver outputs IO = ?6.0 mA IO = ?7.8 mA LOW-level output voltage VI = VIH or VIL all outputs IO = 20 ?A 4.5 6.0 3.84 5.34 4.32 5.81 ? ? V V 4.5 6.0 3.84 5.34 4.32 5.81 ? ? V V V OL 2.0 4.5 6.0 ? ? ? 0 0 0 0.1 0.1 0.1 V V V Q7’ standard output IO = 4.0 mA IO = 5.2 mA Qn bus driver outputs IO = 6.0 mA IO = 7.8 mA input leakage current 3-state output OFF-state current quiescent supply current VI = VCC or GND VI = VIH or VIL; VO = VCC or GND VI = VCC or GND; IO = 0 4.5 6.0 ? ? 0.15 0.16 0.33 0.33 V V 4.5 6.0 6.0 6.0 ? ? ? ? 0.16 0.16 ? ? 0.33 0.33 ?1.0 ?5.0 V V ?A ?A

ILI II OZ 6.0 ? ? 80 ?A CC SYMBOL TEST CONDITIONS PARAMETER OTHER VCC (V) MIN. TYP. MAX. UNIT Tamb = ?40 to +125 ?C VIH HIGH-level input voltage V 2.0 4.5 1.5 3.15 ? ? ? ? V V V 6.0 4.2 ? ? 0.5 1.35 IL LOW-level input voltage 2.0 4.5 ? ? ? ? ? V V V V 6.0 ? 1.8 OH HIGH-level output voltage VI = VIH or VIL all outputs IO = ?20 ?A 2.0 4.5 6.0 1.9 4.4 5.9 ? ? ? ? ? ? V V V Q7’ standard output IO = ?4.0 mA IO = ?5.2 mA Qn bus driver outputs IO = ?6.0 mA IO = ?7.8 mA LOW-level output voltage VI = VIH or VIL all outputs IO = 20 ?A Q7’ standard output IO = 4.0 mA Qn bus driver outputs IO = 6.0 mA input leakage current 3-state output OFF-state current quiescent supply current VI = VCC or GND VI = VIH or VIL; VO = VCC or GND VI = VCC or GND; IO = 0 4.5 6.0 3.7 5.2 ? ? ? ? V V 4.5 6.0 3.7 5.2 ? ? ? ? V V V OL 4.5 ? ? 0.1 V 4.5 ? ? 0.4 V II 4.5 5.5 5.5 ? ? ? ? ? ? 0.4 ?1.0 ?10.0 V ?A ?A LI OZI 5.5 ? ? 160 ?A CC Note

1. All typical values are measured at Tamb = 25 ?C.

Type 74HCT TEST CONDITIONS

At recommended operating conditions; voltages are referenced to GND (ground = 0 V); tr = tf = 6 ns; CL = 50 pF. SYMBOL PARAMETER OTHER VCC (V) MIN. TYP. MAX. UNIT Tamb = ?40 to +85 ?C; note 1 VIH HIGH-level input voltage VIL LOW-level input voltage 4.5 to 5.5 2.0 1.6 ? V 4.5 to 5.5 ? 1.2 0.8 V VOH HIGH-level output voltage VI = VIH or VIL all outputs IO = ?20 ?A Q7’ standard output IO = ?4.0 mA IO = ?6.0 mA 4.5 4.4 4.5 ? V 4.5 3.84 4.32 ? V VQn bus driver outputs 4.5 LOW-level output voltage VI = VIH or VIL all outputs IO = 20 ?A Q7’ standard output IO = 4.0 mA IO = 6.0 mA input leakage current 3-state output OFF-state current quiescent supply current additional supply current per input VI = VCC or GND VI = VIH or VIL; VO = VCC or GND VI = VCC or GND; IO = 0 VI = VCC ? 2.1 V; IO = 0; note 2 3.7 4.32 ? V OL 4.5 ? 0 0.33 V 4.5 ? 0.15 0.33 V IIQn bus driver outputs 4.5 5.5 5.5 ? ? ? 0.16 ? ? 0.33 ?1.0 ?5.0 V ?A ?A LI OZI 5.5 ? ? 80 ?A CC 100 450 ?A ?ICC 4.5 to 5.5 ?

SYMBOL

TEST CONDITIONS PARAMETER OTHER VCC (V) MIN. TYP. MAX. UNIT Tamb = ?40 to +125 ?C VIH HIGH-level input voltage VIL LOW-level input voltage 4.5 to 5.5 2.0 ? ? V 4.5 to 5.5 ? ? 0.8 V VOH HIGH-level output voltage VI = VIH or VIL all outputs IO = ?20 ?A Q7’ standard output IO = ?4.0 mA IO = ?6.0 mA 4.5 4.4 ? ? V 4.5 3.7 ? ? V VQn bus driver outputs 4.5 LOW-level output voltage VI = VIH or VIL all outputs IO = 20 ?A Q7’ standard output IO = 4.0 mA IO = 6.0 mA input leakage current 3-state output OFF-state current quiescent supply current additional supply current per input VI = VCC or GND VI = VIH or VIL; VO = VCC or GND VI = VCC or GND; IO = 0 VI = VCC ? 2.1 V; IO = 0; note 2 3.7 ? ? V OL 4.5 ? ? 0.1 V 4.5 ? ? 0.4 V IIQn bus driver outputs 4.5 5.5 5.5 ? ? ? ? ? ? 0.4 ?1.0 ?10.0 V ?A ?A LI OZI 5.5 ? ? 160 ?A CC?I ? 490 ?A CC4.5 to 5.5 ? Notes：74HC595PW

1. All typical values are measured at Tamb = 25 ?C.

2. The value of additional quiescent supply current (?ICC) for a unit load of 1 is given here. To determine ?ICC per

input, multiply this value by the unit load coefficient per input pin:

a. pin DS: 0.25

b. pins MR, SH_CP, ST_CP and OE: 1.50.

AC CHARACTERISTICS

Family 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF. SYMBOL

TEST CONDITIONS PARAMETER WAVEFORMS VCC (V) MIN. TYP. MAX. UNIT Tamb = 25 ?C tPHLPLH /t propagation delay SH_CP to Q7’ propagation delay ST_CP to Qn see Fig.7 see Fig.8 2.0 4.5 ? ? 52 19 160 32 ns ns ns 6.0 ? 15 27 175 2.0 ? 55 20 ns ns t 4.5 ? ? 35 30 6.0 16 47 17 ns ns ns PHL propagation delay MR to Q7’ see Fig.10 2.0 4.5 ? ? ? 175 35 30 tPZHPZL /t 6.0 2.0 4.5 14 47 17 ns ns ns 3-state output enable time OE to Qn see Fig.11 ? ? ? 150 30 26 tPHZPLZ /t 6.0 2.0 4.5 14 41 15 ns ns ns 3-state output disable time OE to Qn see Fig.11 ? ? ? 150 30 26 t 6.0 2.0 4.5 12 17 6 ns ns ns W shift clock pulse width HIGH or LOW storage clock pulse width HIGH or LOW master reset pulse width LOW see Fig.7 see Fig.8 75 15 13 ? ? ? 6.0 5 11 ns ns 2.0 75 15 ? ? 4.5 4 3 ns ns 6.0 13 75 ? ? see Fig.10 2.0 4.5 17 6.0 ns ns t 15 13 ? ? 6.0 5.0 11 4.0 ns ns ns su set-up time DS to SH_CP set-up time SH_CP to ST_CP see Fig.9 see Fig.8 2.0 4.5 50 10 9.0 ? ? ? 6.0 3.0 22 ns ns 2.0 75 15 ? ? t 4.5 8 7 ns ns 6.0 13 +3 +3 ? ? ? h hold time DS to SH_CP see Fig.9

2.0 4.5 ?6 ?2 ?2 ns ns ns 6.0 +3 ?

SYMBOL t PARAMETER TEST CONDITIONS WAVEFORMS VCC (V) MIN. TYP. MAX. UNIT ns ns rem removal time MR to SH_CP see Fig.10 f 2.0 4.5 +50 +10 ?19 ?7 ? ? ? 6.0 +9 ?6 30 91 ns MHz MHz max maximum clock pulse frequency SH_CP or ST_CP see Figs 7 and 8 2.0 4.5 9 30 35 ? ? ? 6.0 108 MHz Tamb = ?40 to +85 ?C tPHLPLH /t propagation delay SH_CP to Q7’ see Fig.7 see Fig.8 2.0 4.5 ? ? ? ? 200 40 ns ns ns 6.0 ? ? 34 220 propagation delay ST_CP to An 2.0 ? ? ? ns ns t 4.5 ? ? 44 37 6.0 ? ? ? ns ns ns PHL propagation delay MR to Q7’ see Fig.10 2.0 4.5 ? ? ? 220 44 37 tPZHPZL /t6.0 2.0 4.5 ? ? ? ns ns ns 3-state output enable time OE to Qn see Fig.11 ? ? ? 190 38 33 tPHZPLZ /t6.0 2.0 4.5 ? ? ? ns ns ns 3-state output disable time OE to Qn see Fig.11 ? ? ? 190 38 33 6.0 2.0 4.5 ? ? ? ns ns ns tW shift clock pulse width HIGH or LOW see Fig.7 see Fig.8 95 19 16 ? ? ? 6.0 ? ? ns ns storage clock pulse width HIGH or LOW 2.0 95 19 ? ? 4.5 ? ? ns ns 6.0 16 95 ? ? master reset pulse width see Fig.10 2.0 4.5 ? ? ns ns LOW t 19 16 ? ? 6.0 ? ? ? ns ns ns su set-up time DS to SH_CP see Fig.9

see Fig.8 2.0 4.5 65 13 11 ? ? ? 6.0 ? ? ns ns set-up time SH_CP to ST_CP 2.0 95 19 ? ? 4.5 ? ? ns ns 6.0 16 ?

SYMBOL PARAMETER TEST CONDITIONS WAVEFORMS VCC (V) MIN. TYP. MAX. UNIT ns ns th hold time DS to SH_CP see Fig.9 t 2.0 4.5 3 3 ? ? ? ? ? 6.0 3 ? ? ? ns ns ns rem removal time MR to SH_CP see Fig.10 f 2.0 4.5 65 13 11 ? ? ? 6.0 ? ? ? ns MHz MHz max maximum clock pulse frequency see Figs 7 and 8 2.0 4.5 4.8 24 28 ? ? ? SH_CP or ST_CP 6.0 ? MHz Tamb = ?40 to +125 ?C tPHLPLH /t propagation delay SH_CP to Q7’ see Fig.7 see Fig.8 2.0 4.5 ? ? ? ? 240 48 ns ns ns 6.0 ? ? 41 265 propagation delay ST_CP to Qn 2.0 ? ? ? ns ns t 4.5 ? ? 53 45 6.0 ? ? ? ns ns ns PHL propagation delay MR to Q7’ see Fig.10 2.0 4.5 ? ? ? 265 53 45 tPZHPZL /t6.0 2.0 4.5 ? ? ? ns ns ns 3-state output enable time OE to Qn see Fig.11 ? ? ? 225 45 38 tPHZPLZ /t6.0 2.0 4.5 ? ? ? ns ns ns 3-state output disable time OE to Qn see Fig.11 ? ? ? 225 45 38 6.0 2.0 4.5 ? ? ? ns ns ns tW shift clock pulse width HIGH or LOW see Fig.7

see Fig.8 110 22 19 ? ? ? 6.0 ? ? ns ns storage clock pulse width HIGH or LOW 2.0 110 22 ? ? 4.5 ? ? ns ns 6.0 19 110 ? ? master reset pulse width see Fig.10 2.0 4.5 ? ? ns ns LOW 22 19 ? ? 6.0 ? ns

SYMBOL

TEST CONDITIONS t PARAMETER set-up time DS to SH_CP WAVEFORMS VCC (V) MIN. TYP. MAX. UNIT ns ns su see Fig.9 2.0 4.5 75 15 ? ? ? ? ? 6.0 13 ? ? ns ns set-up time see Fig.8 2.0 110 22 ? ? SH_CP to ST_CP 4.5 ? ? ns ns 6.0 19 3 3 ? ? ? th hold time DS to SH_CP see Fig.9 t 2.0 4.5 ? ? ? ns ns ns 6.0 3 75 15 ? ? ? rem removal time MR to SH_CP see Fig.10 f 2.0 4.5 ? ? ? ns ns ns 6.0 13 4 20 ? ? ? max maximum clock pulse frequency SH_CP or ST_CP see Figs 7 and 8 2.0 4.5 6.0 ? ? ? MHz MHz MHz

24 ?

Family 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF. SYMBOL

TEST CONDITIONS PARAMETER WAVEFORMS VCC (V) MIN. TYP. MAX. UNIT Tamb = 25 ?C t/tPHLPLH propagation delay SH_CP to Q7’ see Fig.7 4.5 ? 25 42 ns propagation delay ttt ST_CP to Qn see Fig.8 4.5 ? 24 40 ns PHL PZHPZL PHZPLZ propagation delay MR to Q7’ OE to Qn OE to Qn see Fig.10 4.5 ? 23 40 ns ns /t/t 3-state output enable time see Fig.11 4.5 ? 21 35 30 3-state output disable time see Fig.11 4.5 ? 18 6 ns ns tW shift clock pulse width HIGH or LOW see Fig.7 4.5 16 16 ? storage clock pulse width HIGH or LOW see Fig.8 4.5 5 ? ns master reset pulse width t LOW see Fig.10 4.5 20 8 ? ns su set-up time DS to SH_CP see Fig.9 set-up time SH_CP to ST_CP see Fig.8 4.5 4.5 16 16 5 8 ? ? ns ns th t rem max hold time DS to SH_CP removal time MR to SH_CP see Fig.9 see Fig.10 4.5 4.5 +3 +10 ?2 ?7 ? ? ns ns MHz f maximum clock pulse frequency see Figs 7 and 8 4.5 30 52 ? SH_CP or ST_CP Tamb = ?40 to +85 ?C t/tPHLPLH propagation delay SH_CP to Q7’ see Fig.7 4.5 ? ? 53 ns tttpropagation delay ST_CP to Qn see Fig.8 4.5 ? ? 50 ns PHL PZHPZL PHZPLZ propagation delay MR to Q7’ OE to Qn OE to Qn see Fig.10 4.5 ? ? 50 ns ns /t/t 3-state output enable time see Fig.11 4.5 ? ? 44 38 3-state output disable time see Fig.11 4.5 ? ? ns

SYMBOL PARAMETER TEST CONDITIONS WAVEFORMS VCC (V) MIN. TYP. MAX. UNIT ns tW shift clock pulse width HIGH or LOW see Fig.7 4.5 20 ? ? ? storage clock pulse width HIGH or LOW see Fig.8 4.5 20 ? ns master reset pulse width t LOW see Fig.10 4.5 25 ? ? ns su set-up time DS to SH_CP see Fig.9 set-up time SH_CP to ST_CP th tfsee Fig.8 4.5 4.5 20 20 ? ? ? ? ns ns rem max hold time DS to SH_CP removal time MR to SH_CP see Fig.9 see Fig.10 4.5 4.5 3 13 ? ? ? ? ns ns MHz maximum clock pulse frequency see Figs 7 and 8 4.5 24 ? ? SH_CP or ST_CP Tamb = ?40 to +125 ?C t/tPHLPLH propagation delay SH_CP to Q7’ see Fig.7 4.5 ? ? 63 ns tttpropagation delay ST_CP to Qn see Fig.8 4.5 ? ? 60 ns PHL PZHPZL PHZPLZ propagation delay MR to Q7’ OE to Qn OE to Qn see Fig.10 4.5 ? ? 60 ns ns /t/t 3-state output enable time see Fig.11 4.5 ? ? 53 45 3-state output disable time see Fig.11 4.5 ? ? ? ns ns tW shift clock pulse width HIGH or LOW see Fig.7 4.5 24 24 ? storage clock pulse width HIGH or LOW see Fig.8 4.5 ? ? ns master reset pulse width t LOW see Fig.10 4.5 30 ? ? ns su set-up time DS to SH_CP see Fig.9 set-up time SH_CP to ST_CP see Fig.8 4.5 4.5 24 24 ? ? ? ? ns ns th t rem max hold time DS to SH_CP removal time MR to SH_CP see Fig.9 see Fig.10 4.5 4.5 3 15 ? ? ? ? ns ns MHz f maximum clock pulse frequency see Figs 7 and 8 4.5 20 ? ?

SH_CP or ST_CP

AC WAVEFORMS（74HC595PW）

SH_CP input

VM

1/fmax

t

Q7' output

t

tW PLH

PHL 90% 10%

VM

MSA699

t

TLH

t

THL

74HC595: VM = 50%; VI = GND to VCC.

74HCT595: VM = 1.3 V; VI = GND to 3 V.

Fig.7 Waveforms showing the clock (SH_CP) to output (Q7’) propagation delays, the shift clock pulse width

and maximum shift clock frequency.

SH_CP input

V

M

t

ST_CP input

su

1/f

V

M tW

max

t

Qn output

PLH

VM

t

PHL

MSA700

74HC595: VM = 50%; VI = GND to VCC.

74HCT595: VM = 1.3 V; VI = GND to 3 V.

Fig.8 Waveforms showing the storage clock (ST_CP) to output (Qn) propagation delays, the storage

clock pulse width and the shift clock to storage clock set-up time.

handbook, full pagewidth SH_CP input VM tsu tth su t 74HC595: VM = 50%; VI = GND to VCC. Q7' output DS input h VM VM MLB196 74HCT595: VM = 1.3 V; VI = GND to 3 V. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig.9 Waveforms showing the data set-up and hold times for the DS input. MR input VM tW SH_CP input trem V M Q7' output t PHL V M MLB197 74HC595: VM = 50%; VI = GND to VCC. 74HCT595: VM = 1.3 V; VI = GND to 3 V.

Fig.10 Waveforms showing the Master Reset (MR) pulse width, the master reset to output (Q7’) propagation delay and the master reset to shift clock (SH_CP) removal time. handbook, full pagewidth

OE input tr tf 90% 10% VM t PLZ Qn output LOW-to-OFF OFF-to-LOW t PZL M V 10% t PHZ t90% PZH Qn output HIGH-to-OFF OFF-to-HIGH disabled VM outputs enabled MSA697 74HC595: VM = 50%; VI = GND to VCC. outputs outputs enabled

74HCT595: VM = 1.3 V; VI = GND to 3 V. Fig.11 Waveforms showing the 3-state enable and disable times for input OE. handbook, full pagewidth

V

GENERATOR

PULSE

VCC

VV

O

CC

I

D.U.T

RL = 1 k?

R

T

C

L

50 pF

MGK563

TEST tPLH/tPHL

SWITCH

open

Definitions for test circuit: RL = Load resistor.

CL = Load capacitance including jig and probe capacitance.

tPLZ/tPZL tPHZ/tPZH

V

CC GND

Fig.12 Test circuit for 3-state outputs.

RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.

PACKAGE OUTLINES

DIP16: plastic dual in-line package; 16 leads (300 mil) D

SOT38-4

seating plane ME L Z A2 A A1 w M c e b b1 16 b2 MH (e1) UNIT 9 pin 1 index E 1 8 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) A max. 4.2 A 1 min. 0.51 A 2 max. 3.2 b mm 1.73 1.30 0.068 0.051 inches 0.17 0.02 0.13 0.53 0.38 0.021 0.015 1b 1.25 0.85 0.049 0.033 2b c D (1) E (1) e e 1 L M 0.36 0.23 0.014 0.009 19.50 18.55 0.77 0.73 6.48 6.20 0.26 0.24 2.54 7.62 3.60 3.05 0.14 0.12 0.1 0.3 8.25 7.80 0.32 0.31 E 10.0 8.3 0.39 0.33 HM w max. Z (1) 0.254 0.76 0.01 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT38-4 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE

95-01-14 03-02-13

SO16: plastic small outline package; 16 leads; body width 3.9 mm

D

SOT109-1

E A

X

y

c

HE

Z 16

v M A

9

Q

(A3)

θ A

pin 1 index

A2

A

1

L detail X

L p

8

1

e

w M

b p

0 2.5 5 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. 1.75 A1 A2 A3 bp c 0.25 0.19 D (1) E (1) e HE L Lp Q 0.7 0.6 v 0.25 w 0.25 y 0.1 Z (1) θ mm 0.25 0.10 1.45 1.25 0.25 0.49 0.36 10.0 9.8 4.0 3.8 0.16 0.15 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.3 0.028 0.012

inches 0.069 0.010 0.057 0.019 0.0100 0.39 0.004 0.049 0.01 0.014 0.0075 0.38 0.05 0.244 0.039 0.028 0.228 0.041 0.016 0.020 0.01 0.01 0.004 8 o 0o Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE

99-12-27 03-02-19

SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm

D

E

A

SOT338-1

X

c

y

HE

v M A

Z

9

16

A2

pin 1 index

A1

Q

(A3)

A

L

8

w M

L p

θ

1

detail X

e

bp

0 2.5 scale 5 mm

DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 A2 A3 bp 0.38 c 0.20 0.09 D (1) E (1) 0.21 0.05 1.80 1.65 6.4 6.0 e HE L Lp 5.4 5.2 7.9 7.6 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) θ 1.00 0.55 8o

0.25 0.25 0.65 1.25 0o Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE REFERENCES VERSION SOT338-1 IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION ISSUE DATE

99-12-27 03-02-19

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

D E

SOT403-1

A

X

y

c

HE

v M A

Z

9

16

2

Q

A

pin 1 index

A1

(A3)

A

θ

L L p

1

e

8

w M bp

detail X

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions) UNIT A max. 1.1 A1 A2 A3 bp c 0.1 D (1) E (2) e HE L 1 Lp Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) θ 0o 8o

mm 0.15 0.05 0.95 0.80 0.30 0.2 5.1 4.9 4.5 4.3 6.6 6.2 0.75 0.50 0.40 0.06 0.25 0.19 0.65 Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE

REFERENCES VERSION SOT403-1 IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE

99-12-27 03-02-18

DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm

D B A

A A1 E c

detail X terminal 1 index area

C e1 terminal 1

index area

e y yb v M C A B 1 C w M C

2 7 L

1 8

e Eh

16 9

10 15

Dh

X

2.5 5 mm 0

scale

DIMENSIONS (mm are the original dimensions) A(1) e1 y1 D(1) Dh E(1) Eh UNIT max. A1 b c e L v w y 0.05 0.30 3.6 2.15 2.6 1.15 0.5 mm 1 0.2 0.5 2.5 0.1 0.05 0.05 0.1 0.00 0.18 3.4 1.85 2.4 0.85 0.3

Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

EUROPEAN OUTLINE REFERENCES ISSUE DATE VERSION PROJECTION IEC JEDEC JEITA 02-10-17 SOT763-1 - - - MO-241 - - - 03-01-27

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