AD7708/AD7718
AD7708/AD7718 to 68HC11 InterfaceAD7708/AD7718-to-8051 InterfaceFigure 19 shows an interface between the AD7708/AD7718 andthe 68HC11 microcontroller. The diagram shows the minimum(3-wire) interface with CS on the AD7708/AD7718 hardwiredlow. In this scheme, the RDY bit of the Status Register ismonitored to determine when the Data Register is updated.An alternative scheme, which increases the number of inter-face lines to four, is to monitor the RDY output line from theAD7708/AD7718. The monitoring of the RDY line can be donein two ways. First, RDY can be connected to one of the 68HC11’sport bits (such as PC0), which is configured as an input. Thisport bit is then polled to determine the status of RDY. Thesecond scheme is to use an interrupt driven system, in whichcase the RDY output is connected to the IRQ input of the68HC11. For interfaces that require control of the CS input onthe AD7708/AD7718, one of the port bits of the 68HC11 (suchas PC1), which is configured as an output, can be used to drivethe CS input.VDD68HC11SSRESETVDD AD7708/AD7718SCKSCLKMISODOUTMOSIDINCSAn interface circuit between the AD7708/AD7718 and the8XC51 microcontroller is shown in Figure 20. The diagramshows the minimum number of interface connections with CSon the AD7708/AD7718 hardwired low. In the case of the8XC51 interface the minimum number of interconnects is justtwo. In this scheme, the RDY bit of the Status Register ismonitored to determine when the Data Register is updated. Thealternative scheme, which increases the number of interfacelines to three, is to monitor the RDY output line from theAD7708/AD7718. The monitoring of the RDY line can be donein two ways. First, RDY can be connected to one of the 8XC51’sport bits (such as P1.0) which is configured as an input. Thisport bit is then polled to determine the status of RDY. Thesecond scheme is to use an interrupt-driven system, in whichcase the RDY output is connected to the INT1 input of the8XC51. For interfaces that require control of the CS input onthe AD7708/AD7718, one of the port bits of the 8XC51 (suchas P1.1), which is configured as an output, can be used to drivethe CS input. The 8XC51 is configured in its Mode 0 serialinterface mode. Its serial interface contains a single data line. Asa result, the DOUT and DIN pins of the AD7708/AD7718 shouldbe connected together with a 10 k? pull-up resistor. The serialclock on the 8XC51 idles high between data transfers. The8XC51 outputs the LSB first in a write operation, while theAD7708/AD7718 expects the MSB first so the data to be trans-mitted has to be rearranged before being written to the outputserial register. Similarly, the AD7708/AD7718 outputs the MSBfirst during a read operation while the 8XC51 expects the LSBfirst. Therefore, the data read into the serial buffer needs to berearranged before the correct data word from the AD7708/AD7718 is available in the accumulator.8XC51DVDDDVDDRESET10k?P3.0DOUT AD7708/AD7718Figure 19.AD7708/AD7718-to-68HC11 InterfaceThe 68HC11 is configured in the master mode with its CPOLbit set to a Logic 1 and its CPHA bit set to a Logic 1. When the68HC11 is configured like this, its SCLK line idles high betweendata transfers. The AD7708/AD7718 is not capable of full duplexoperation. If the AD7708/AD7718 is configured for a writeoperation, no data appears on the DOUT lines even when theSCLK input is active. Similarly, if the AD7708/AD7718 is config-ured for a read operation, data presented to the part on the DINline is ignored even when SCLK is active.DINP3.1SCLKCSFigure 20.AD7708/AD7718-to-8XC51 InterfaceREV. 0–35–
AD7708/AD7718
AD7708/AD7718-to-ADSP-2103/ADSP-2105 InterfaceBASIC CONFIGURATIONFigure 21 shows an interface between the AD7708/AD7718 andthe ADSP-2103/ADSP-2105 DSP processor. In the interfaceshown, the RDY bit of the Status Register is again monitored todetermine when the Data Register is updated. The alternativescheme is to use an interrupt-driven system, in which case theRDY output is connected to the IRQ2 input of the ADSP-2103/ADSP-2105. The serial interface of the ADSP-2103/ADSP-2105is set up for alternate framing mode. The RFS and TFS pins ofthe ADSP-2103/ADSP-2105 are configured as active low outputsand the ADSP-2103/ADSP-2105 serial clock line, SCLK, is alsoconfigured as an output. The CS for the AD7708/AD7718 isactive when either the RFS or TFS outputs from the ADSP-2103/ADSP-2105 are active. The serial clock rate on the ADSP-2103/ADSP-2105 should be limited to 3MHz to ensure correctoperation with the AD7708/AD7718.DVDD ADSP-2103/ADSP-2105 AD7708/AD7718RESETThe basic connection diagram for the AD7708/AD7718 in 10-channel mode is shown in Figure 22. This shows both the AVDDand DVDD pins of the converters being driven from the analog5V supply. Some applications will have AVDD and DVDD drivenfrom separate supplies. AVDD and DVDD can be operated inde-pendently of each other, allowing the device to be operated with5 V analog supply and 3 V digital supply or vice versa. The partscan be operated in 8- or 10-channel configurations. In 8-channelmode the user has two reference input options. This allows theuser to operate some channels in ratiometric mode and othersin absolute measurement mode. In 10-channel mode only onereference option is available. An AD780/REF195, precision 2.5 Vreference, provides the reference source for the part. A quartzcrystal or ceramic resonator provides the 32.768 kHz masterclock source for the part. In some cases, it will be necessary toconnect capacitors on the crystal or resonator to ensure that itdoes not oscillate at overtones of its fundamental operating fre-quency. The values of capacitors will vary, depending on themanufacturer’s specifications.ANALOG 5VSUPPLY10?F0.1?F0.1?F5VRESETCSCHIPSELECTRECEIVE(READ)SERIALDATA(WRITE)SERIALCLOCKRFSTFSCSAIN1AVDDAIN2AIN3DVDDDRDOUTDTDINAIN4AIN5 AD7708/AD7718DOUTSCLKSCLKAIN6AIN7DINFigure 21.AD7708/AD7718-to-ADSP-2103/ADSP-2105InterfaceAIN8AIN9AIN10AINCOMANALOG 5VSUPPLY10?FREF1IN(+)0.1?FVINVOUTREF1IN(–)SCLKP1P2MCLKINMCLKOUT32kHzCRYSTALAD780/REF195AGNDDGNDGNDFigure 22.Basic Configuration for 10-Channel Mode–36–REV. 0
半导体传感器AD7730BRZ中文规格书 - 图文
